Lines Matching +full:1 +full:qav
181 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
189 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
196 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
220 #define E1000_PCS_LCTL_FLV_LINK_UP 1
232 #define E1000_PCS_LSTS_LINK_OK 1
239 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
240 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
243 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
260 #define HALF_DUPLEX 1
402 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
406 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
484 #define E1000_ERR_NVM 1
552 #define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */
555 #define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */
557 #define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
565 #define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
569 #define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
570 #define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */
571 #define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
581 #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
584 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
585 #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
586 #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
587 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
588 #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
589 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
591 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
593 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
594 #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
596 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
598 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
599 #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
601 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
603 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
604 #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
606 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
608 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
609 #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
616 #define E1000_MEDIA_PORT_COPPER 1
651 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
655 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
656 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
662 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
682 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
684 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
696 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
711 /* NVM Addressing bits based on type 0=small, 1=large */
746 #define E1000_NVM_RW_REG_START 1 /* Start operation */
899 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
900 /* 1=CLK125 low, 0=CLK125 toggling */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
912 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
915 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
916 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
917 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
919 * 1 = 50-80M
931 /* 1 = Lost lock detect enabled.
934 * within 1ms in 1000BASE-T
951 #define I347AT4_PCDL1 0x11 /* Pair 1 PHY Cable Diagnostics Length */
974 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1001 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
1019 #define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
1022 #define E1000_PCS_STATUS_ADDR_I354 1
1047 /* TX Qav Control fields */
1068 /* TX Qav Credit Control fields */