intel/igb/e1000_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
188 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
245 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
257 #define SPEED_100   100
271 /* 1000/H is not supported, nor spec-compliant. */
305 #define E1000_TCTL_EN     0x00000002    /* enable tx */
309 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
321 #define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coal Tx Threshold */
405 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
406 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
407 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
408 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
505 /* Number of 100 microseconds we wait for PCI Express master disable */
508 #define PHY_CFG_TIMEOUT             100
516 #define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
517 #define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
668 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
669 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
673 /* Link Partner Ability Register (Base Page) */
679 /* 1000BASE-T Control Register */
687 /* 1000BASE-T Status Register */
699 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
700 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909  * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
919  * 1 = 50-80M
920  * 2 = 80-110M
921  * 3 = 110-140M
934  * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1002 #define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
1003 #define E1000_EEER_TX_LPI_EN         0x00010000  /* EEE Tx LPI Enable */
1019 #define E1000_EEE_ADV_100_SUPPORTED	BIT(1)   /* 100BaseTx EEE Supported */
1023 #define E1000_PCS_STATUS_TX_LPI_IND	0x0200     /* Tx in LPI state */
1036 /* Tx Rate-Scheduler Config fields */
1047 /* TX Qav Control fields */
1053 /* Fetch Time Delta - bits 31:16
1068 /* TX Qav Credit Control fields */