intel/igb/e1000_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
246 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
258 #define SPEED_1000  1000
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
449 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
666 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
667 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
673 /* Link Partner Ability Register (Base Page) */
679 /* 1000BASE-T Control Register */
680 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
681 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
687 /* 1000BASE-T Status Register */
692 /* PHY 1000 MII Register/Bit Definitions */
699 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
700 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
713 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909  * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
919  * 1 = 50-80M
920  * 2 = 80-110M
921  * 3 = 110-140M
926 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
934  * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1020 #define E1000_EEE_ADV_1000_SUPPORTED	BIT(2)   /* 1000BaseT EEE Supported */
1036 /* Tx Rate-Scheduler Config fields */
1053 /* Fetch Time Delta - bits 31:16
1063  * XXX: We are configuring the max value here since we couldn't come up