Lines Matching +full:queue +full:- +full:pkt +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
58 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
62 /* Receive Descriptor - Advanced */
92 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
95 /* Transmit Descriptor - Advanced */
117 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
141 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
142 /* Tx Queue Arbitration Priority 0=low, 1=high */
145 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
151 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
152 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
153 #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
154 #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
155 #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
165 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
167 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
245 /* RX packet buffer size defines */