intel/ice/ice_ptp_hw.h

1 /* SPDX-License-Identifier: GPL-2.0 */
67  * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
115  * different link speeds, either the deskew marker for multi-lane link speeds
116  * or the Reed Solomon gearbox marker for RS-FEC.
136  * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
200  * struct ice_cgu_pll_params_e82x - E82X CGU parameters
201  * @refclk_pre_div: Reference clock pre-divisor
202  * @feedback_div: Feedback divisor
224 	ICE_RCLKA_PIN = 0,		/* SCL pin */
225 	ICE_RCLKB_PIN,			/* SDA pin */
291  * struct ice_cgu_pll_params_e825c - E825C CGU parameters
294  * @tspll_fbdiv_intgr: TS PLL integer feedback divide
295  * @tspll_fbdiv_frac:  TS PLL fractional feedback divide
356  * ice_e82x_time_ref - Get the current TIME_REF from capabilities
363 	return hw->func_caps.ts_func_info.time_ref;  in ice_e82x_time_ref()
367  * ice_set_e82x_time_ref - Set new TIME_REF
377 	hw->func_caps.ts_func_info.time_ref = time_ref;  in ice_set_e82x_time_ref()
408 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
410 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
411 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
413 		      enum dpll_lock_status last_dpll_state, u8 *pin,
436  * ice_get_base_incval - Get base clock increment value
443 	switch (hw->ptp.phy_model) {  in ice_get_base_incval()
487 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
488 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
692 /* E810T SMA controller pin control */
714 /* E810T PCA9575 IO controller pin control */
784 /* 1-step PTP config */