Lines Matching +full:0 +full:x49c
133 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
224 ICE_RCLKA_PIN = 0, /* SCL pin */
234 ZL_REF0P = 0,
248 ZL_OUT0 = 0,
259 SI_REF0P = 0,
271 SI_OUT0 = 0,
328 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
429 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
430 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
431 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
432 #define ICE_ETH56G_NOMINAL_THRESH4 0x7777
433 #define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
439 * Return: base clock increment value for supported PHYs, 0 otherwise
451 return 0; in ice_get_base_incval()
457 #define ICE_PTP_CLOCK_INDEX_0 0x00
458 #define ICE_PTP_CLOCK_INDEX_1 0x01
465 #define GLTSYN_CMD_INIT_TIME BIT(0)
467 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
473 #define PHY_CMD_INIT_TIME BIT(0)
475 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
476 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
477 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
479 #define TS_CMD_MASK_E810 0xFF
480 #define TS_CMD_MASK 0xF
481 #define SYNC_EXEC_CMD 0x3
482 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
485 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
486 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
487 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
488 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
491 #define Q_0_BASE 0x94000
492 #define Q_1_BASE 0x114000
495 #define Q_REG_TS_CTRL 0x618
496 #define Q_REG_TS_CTRL_S 0
497 #define Q_REG_TS_CTRL_M BIT(0)
500 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
501 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
504 #define Q_REG_FIFO23_STATUS 0xCF8
505 #define Q_REG_FIFO01_STATUS 0xCFC
506 #define Q_REG_FIFO02_S 0
507 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
509 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
512 #define Q_REG_TX_MEM_GBL_CFG 0xC08
513 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
514 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
515 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
516 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
520 #define Q_REG_TX_MEMORY_BANK_START 0xA00
523 #define P_0_BASE 0x80000
524 #define P_4_BASE 0x106000
527 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
528 #define P_REG_RX_TIMER_INC_PRE_U 0x470
529 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
530 #define P_REG_TX_TIMER_INC_PRE_U 0x450
533 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
534 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
535 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
536 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
539 #define P_REG_RX_CAPTURE_L 0x4D8
540 #define P_REG_RX_CAPTURE_U 0x4DC
541 #define P_REG_TX_CAPTURE_L 0x4B4
542 #define P_REG_TX_CAPTURE_U 0x4B8
545 #define P_REG_TIMETUS_L 0x410
546 #define P_REG_TIMETUS_U 0x414
548 #define P_REG_40B_LOW_M GENMASK(7, 0)
552 #define P_REG_WL 0x40C
554 #define PTP_VERNIER_WL 0x111ed
557 #define P_REG_PS 0x408
558 #define P_REG_PS_START_S 0
559 #define P_REG_PS_START_M BIT(0)
570 #define P_REG_TX_OV_STATUS 0x4D4
571 #define P_REG_TX_OV_STATUS_OV_S 0
572 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
573 #define P_REG_RX_OV_STATUS 0x4F8
574 #define P_REG_RX_OV_STATUS_OV_S 0
575 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
578 #define P_REG_TX_OR 0x45C
579 #define P_REG_RX_OR 0x47C
582 #define P_REG_TOTAL_RX_OFFSET_L 0x460
583 #define P_REG_TOTAL_RX_OFFSET_U 0x464
584 #define P_REG_TOTAL_TX_OFFSET_L 0x440
585 #define P_REG_TOTAL_TX_OFFSET_U 0x444
588 #define P_REG_UIX66_10G_40G_L 0x480
589 #define P_REG_UIX66_10G_40G_U 0x484
590 #define P_REG_UIX66_25G_100G_L 0x488
591 #define P_REG_UIX66_25G_100G_U 0x48C
592 #define P_REG_DESK_PAR_RX_TUS_L 0x490
593 #define P_REG_DESK_PAR_RX_TUS_U 0x494
594 #define P_REG_DESK_PAR_TX_TUS_L 0x498
595 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
596 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
597 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
598 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
599 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
600 #define P_REG_PAR_RX_TUS_L 0x420
601 #define P_REG_PAR_RX_TUS_U 0x424
602 #define P_REG_PAR_TX_TUS_L 0x428
603 #define P_REG_PAR_TX_TUS_U 0x42C
604 #define P_REG_PCS_RX_TUS_L 0x430
605 #define P_REG_PCS_RX_TUS_U 0x434
606 #define P_REG_PCS_TX_TUS_L 0x438
607 #define P_REG_PCS_TX_TUS_U 0x43C
608 #define P_REG_PAR_RX_TIME_L 0x4F0
609 #define P_REG_PAR_RX_TIME_U 0x4F4
610 #define P_REG_PAR_TX_TIME_L 0x4CC
611 #define P_REG_PAR_TX_TIME_U 0x4D0
612 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
613 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
614 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
615 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
616 #define P_REG_LINK_SPEED 0x4FC
617 #define P_REG_LINK_SPEED_SERDES_S 0
618 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
620 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
626 #define P_REG_PMD_ALIGNMENT 0x0FC
627 #define P_REG_RX_80_TO_160_CNT 0x6FC
628 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
629 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
630 #define P_REG_RX_40_TO_160_CNT 0x8FC
631 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
632 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
635 #define P_REG_RX_OV_FS 0x4F8
637 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
640 #define P_REG_TX_TMR_CMD 0x448
641 #define P_REG_RX_TMR_CMD 0x468
644 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
647 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
648 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
651 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
652 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
655 #define E810_ETH_GLTSYN_CMD 0x03000344
658 #define INCVAL_HIGH_M 0xFF
661 #define TS_VALID BIT(0)
662 #define TS_LOW_M 0xFFFFFFFF
663 #define TS_HIGH_M 0xFF
666 #define TS_PHY_LOW_M 0xFF
667 #define TS_PHY_HIGH_M 0xFFFFFFFF
686 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
689 #define LOW_TX_MEMORY_BANK_START 0x03090000
690 #define HIGH_TX_MEMORY_BANK_START 0x03090004
712 #define ICE_PCA9575_P0_IN 0x0
719 #define PHY_REG_TIMETUS_L 0x8
720 #define PHY_REG_TIMETUS_U 0xC
723 #define PHY_PCS_REF_TUS_L 0x18
724 #define PHY_PCS_REF_TUS_U 0x1C
727 #define PHY_PCS_REF_INC_L 0x20
728 #define PHY_PCS_REF_INC_U 0x24
731 #define PHY_REG_RX_TIMER_INC_PRE_L 0x64
732 #define PHY_REG_RX_TIMER_INC_PRE_U 0x68
733 #define PHY_REG_TX_TIMER_INC_PRE_L 0x44
734 #define PHY_REG_TX_TIMER_INC_PRE_U 0x48
737 #define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
738 #define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
739 #define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
740 #define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
743 #define PHY_REG_TX_TMR_CMD 0x40
744 #define PHY_REG_RX_TMR_CMD 0x60
747 #define PHY_REG_TX_OFFSET_READY 0x54
748 #define PHY_REG_RX_OFFSET_READY 0x74
751 #define PHY_REG_TOTAL_TX_OFFSET_L 0x38
752 #define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
753 #define PHY_REG_TOTAL_RX_OFFSET_L 0x58
754 #define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
757 #define PHY_REG_TX_CAPTURE_L 0x78
758 #define PHY_REG_TX_CAPTURE_U 0x7C
759 #define PHY_REG_RX_CAPTURE_L 0x8C
760 #define PHY_REG_RX_CAPTURE_U 0x90
763 #define PHY_REG_TX_MEMORY_STATUS_L 0x80
764 #define PHY_REG_TX_MEMORY_STATUS_U 0x84
767 #define PHY_REG_TS_INT_CONFIG 0x88
770 #define PHY_MAC_XIF_MODE 0x24
771 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
772 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
773 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
774 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
777 #define PHY_GPCS_CONFIG_REG0 0x268
778 #define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
779 #define PHY_GPCS_BITSLIP 0x5C
781 #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
785 #define PHY_PTP_1STEP_CONFIG 0x270
786 #define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
787 #define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
788 #define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
789 #define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
790 #define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
791 #define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
794 #define PHY_TSTAMP_L(x) (((x) * 8) + 0)
797 #define PHY_REG_REVISION 0x85000
799 #define PHY_REG_DESKEW_0 0x94
800 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
805 #define PHY_REG_GPCS_BITSLIP 0x5C
806 #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
807 #define PHY_REVISION_ETH56G 0x10200
808 #define PHY_VENDOR_TXLANE_THRESH 0x2000C
810 #define PHY_MAC_TSU_CONFIG 0x40
811 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
812 #define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
813 #define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
814 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
815 #define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
816 #define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
817 #define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
818 #define PHY_MAC_RX_MODULO 0x44
819 #define PHY_MAC_RX_OFFSET 0x48
820 #define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
821 #define PHY_MAC_TX_MODULO 0x4C
822 #define PHY_MAC_BLOCKTIME 0x50
823 #define PHY_MAC_MARKERTIME 0x54
824 #define PHY_MAC_TX_OFFSET 0x58
826 #define PHY_PTP_INT_STATUS 0x7FD140