Lines Matching +full:ptp +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
141 * +---------------+ +---------------+ +---------------+
143 * +---------------+ +---------------+ +---------------+
149 * +---------------+ +---------------+
151 * +---------------+ +---------------+
162 * - 823.4375 MHz
163 * - 783.36 MHz
164 * - 796.875 MHz
165 * - 816 MHz
166 * - 830.078125 MHz
167 * - 783.36 MHz
183 * - E822 based devices have additional support for fine grained Vernier
185 * - The layout of timestamp data in the PHY register blocks is different
186 * - The way timer synchronization commands are issued is different.
198 * ice_get_ptp_src_clock_index - determine source clock index
206 return hw->func_caps.ts_func_info.tmr_index_assoc; in ice_get_ptp_src_clock_index()
210 * ice_ptp_read_src_incval - Read source timer increment value
229 * ice_read_cgu_reg_e82x - Read a CGU register
261 * ice_write_cgu_reg_e82x - Write a CGU register
292 * ice_clk_freq_str - Convert time_ref_freq to string
318 * ice_clk_src_str - Convert time_ref_src to string
336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
342 * time reference, enabling the PLL which drives the PTP hardware clock.
345 * * %0 - success
346 * * %-EINVAL - input parameters are incorrect
347 * * %-EBUSY - failed to lock TS PLL
348 * * %other - CGU read/write failure
364 return -EINVAL; in ice_cfg_cgu_pll_e82x()
370 return -EINVAL; in ice_cfg_cgu_pll_e82x()
377 return -EINVAL; in ice_cfg_cgu_pll_e82x()
393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
467 return -EBUSY; in ice_cfg_cgu_pll_e82x()
471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
487 * time reference, enabling the PLL which drives the PTP hardware clock.
490 * * %0 - success
491 * * %-EINVAL - input parameters are incorrect
492 * * %-EBUSY - failed to lock TS PLL
493 * * %other - CGU read/write failure
511 return -EINVAL; in ice_cfg_cgu_pll_e825c()
517 return -EINVAL; in ice_cfg_cgu_pll_e825c()
524 return -EINVAL; in ice_cfg_cgu_pll_e825c()
548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e825c()
649 return -EBUSY; in ice_cfg_cgu_pll_e825c()
653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e825c()
663 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
690 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
713 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
722 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; in ice_init_cgu_e82x()
737 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, in ice_init_cgu_e82x()
738 (enum ice_clk_src)ts_info->clk_src); in ice_init_cgu_e82x()
740 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, in ice_init_cgu_e82x()
741 (enum ice_clk_src)ts_info->clk_src); in ice_init_cgu_e82x()
747 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
751 * Return: the source timer command register value for the given PTP timer
788 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
796 * Return: the PHY port timer command register value for the given PTP timer
807 switch (hw->ptp.phy_model) { in ice_ptp_tmr_cmd_to_port_reg()
845 * ice_ptp_src_cmd - Prepare source timer for a timer command
859 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
870 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); in ice_ptp_exec_tmr_cmd()
881 * ice_write_phy_eth56g - Write a PHY port register
901 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; in ice_write_phy_eth56g()
906 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", in ice_write_phy_eth56g()
913 * ice_read_phy_eth56g - Read a PHY port register
933 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; in ice_read_phy_eth56g()
937 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", in ice_read_phy_eth56g()
948 * ice_phy_res_address_eth56g - Calculate a PHY port register address
955 * * %0 - success
956 * * %EINVAL - invalid port number or resource type
965 return -EINVAL; in ice_phy_res_address_eth56g()
973 * ice_write_port_eth56g - Write a PHY port register
981 * * %0 - success
982 * * %EINVAL - invalid port number or resource type
983 * * %other - failed to write to PHY
988 u8 phy_port = port % hw->ptp.ports_per_phy; in ice_write_port_eth56g()
989 u8 phy_idx = port / hw->ptp.ports_per_phy; in ice_write_port_eth56g()
993 if (port >= hw->ptp.num_lports) in ice_write_port_eth56g()
994 return -EINVAL; in ice_write_port_eth56g()
1004 * ice_read_port_eth56g - Read a PHY port register
1012 * * %0 - success
1013 * * %EINVAL - invalid port number or resource type
1014 * * %other - failed to read from PHY
1019 u8 phy_port = port % hw->ptp.ports_per_phy; in ice_read_port_eth56g()
1020 u8 phy_idx = port / hw->ptp.ports_per_phy; in ice_read_port_eth56g()
1024 if (port >= hw->ptp.num_lports) in ice_read_port_eth56g()
1025 return -EINVAL; in ice_read_port_eth56g()
1035 * ice_write_ptp_reg_eth56g - Write a PHY port register
1042 * * %0 - success
1043 * * %EINVAL - invalid port number or resource type
1044 * * %other - failed to write to PHY
1053 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
1061 * * %0 - success
1062 * * %EINVAL - invalid port number or resource type
1063 * * %other - failed to write to PHY
1072 * ice_write_xpcs_reg_eth56g - Write a PHY port register
1079 * * %0 - success
1080 * * %EINVAL - invalid port number or resource type
1081 * * %other - failed to write to PHY
1091 * ice_read_ptp_reg_eth56g - Read a PHY port register
1098 * * %0 - success
1099 * * %EINVAL - invalid port number or resource type
1100 * * %other - failed to read from PHY
1109 * ice_read_mac_reg_eth56g - Read a PHY port register
1116 * * %0 - success
1117 * * %EINVAL - invalid port number or resource type
1118 * * %other - failed to read from PHY
1127 * ice_read_gpcs_reg_eth56g - Read a PHY port register
1134 * * %0 - success
1135 * * %EINVAL - invalid port number or resource type
1136 * * %other - failed to read from PHY
1145 * ice_read_port_mem_eth56g - Read a PHY port memory location
1152 * * %0 - success
1153 * * %EINVAL - invalid port number or resource type
1154 * * %other - failed to read from PHY
1163 * ice_write_port_mem_eth56g - Write a PHY port memory location
1170 * * %0 - success
1171 * * %EINVAL - invalid port number or resource type
1172 * * %other - failed to write to PHY
1181 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
1220 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
1248 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
1260 * * %0 - success
1261 * * %EINVAL - not a 64 bit register
1262 * * %other - failed to read from PHY
1272 return -EINVAL; in ice_read_64b_phy_reg_eth56g()
1294 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
1305 * * %0 - success
1306 * * %EINVAL - not a 64 bit register
1307 * * %other - failed to read from PHY
1317 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
1329 * * %0 - success
1330 * * %EINVAL - not a 40 bit register
1331 * * %other - failed to write to PHY
1342 return -EINVAL; in ice_write_40b_phy_reg_eth56g()
1365 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
1376 * * %0 - success
1377 * * %EINVAL - not a 40 bit register
1378 * * %other - failed to write to PHY
1388 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
1399 * * %0 - success
1400 * * %EINVAL - not a 64 bit register
1401 * * %other - failed to write to PHY
1412 return -EINVAL; in ice_write_64b_phy_reg_eth56g()
1435 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1445 * * %0 - success
1446 * * %EINVAL - not a 64 bit register
1447 * * %other - failed to write to PHY
1457 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1467 * * %0 - success
1468 * * %other - failed to read from PHY
1482 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", in ice_read_ptp_tstamp_eth56g()
1489 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", in ice_read_ptp_tstamp_eth56g()
1504 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1521 * * %0 - success
1522 * * %other - failed to write to PHY
1543 …ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d… in ice_clear_ptp_tstamp_eth56g()
1552 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1559 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_reset_ts_memory_eth56g()
1568 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1576 * * %0 - success
1577 * * %other - failed to write to PHY
1596 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1606 * * %0 - success
1607 * * %other - failed to write to PHY
1619 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_time_eth56g()
1634 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1644 * including the lower sub-nanosecond portion of the port timer.
1649 * * %0 - success
1650 * * %other - failed to write to PHY
1691 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1700 * * %0 - success
1701 * * %other - failed to write to PHY
1708 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_eth56g()
1715 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_adj_eth56g()
1727 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1736 * * %0 - success
1737 * * %other - failed to write to PHY
1743 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_incval_eth56g()
1759 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1768 * * %0 - success
1769 * * %other - failed to read from PHY
1802 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1810 * * %0 - success
1811 * * %other - failed to write to PHY
1839 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1847 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, in ice_phy_get_speed_eth56g()
1848 li->phy_type_high); in ice_phy_get_speed_eth56g()
1862 switch (li->phy_type_low) { in ice_phy_get_speed_eth56g()
1874 if (li->phy_type_high || in ice_phy_get_speed_eth56g()
1875 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) in ice_phy_get_speed_eth56g()
1885 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1893 * * %0 - success
1894 * * %other - PHY read/write failed
1898 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); in ice_phy_cfg_parpcs_eth56g()
1910 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { in ice_phy_cfg_parpcs_eth56g()
1957 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
1962 * * %0 - success
1963 * * %other - PHY read/write failed
1967 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); in ice_phy_cfg_ptp_1step_eth56g()
1968 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1); in ice_phy_cfg_ptp_1step_eth56g()
1973 enable = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_cfg_ptp_1step_eth56g()
1974 peer_delay = hw->ptp.phy.eth56g.peer_delay; in ice_phy_cfg_ptp_1step_eth56g()
1975 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; in ice_phy_cfg_ptp_1step_eth56g()
2017 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { in ice_phy_cfg_ptp_1step_eth56g()
2034 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
2046 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
2058 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
2062 * @fc: FC-FEC enabled
2063 * @rs: RS-FEC enabled
2072 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1); in ice_ptp_calc_bitslip_eth56g()
2073 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); in ice_ptp_calc_bitslip_eth56g()
2100 bitslip = (u32)((s32)bitslip * -1 + 20); in ice_ptp_calc_bitslip_eth56g()
2108 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
2112 * @rs: RS-FEC enabled
2143 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; in ice_ptp_calc_deskew_eth56g()
2148 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
2153 * @fc: FC-FEC enabled
2154 * @rs: RS-FEC enabled
2157 * * %0 - success
2158 * * %other - failed to write to PHY
2168 onestep = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_set_offsets_eth56g()
2169 sfd = hw->ptp.phy.eth56g.sfd_ena; in ice_phy_set_offsets_eth56g()
2170 bs_ds = cfg->rx_offset.bs_ds; in ice_phy_set_offsets_eth56g()
2173 rx_offset = cfg->rx_offset.fc; in ice_phy_set_offsets_eth56g()
2175 rx_offset = cfg->rx_offset.rs; in ice_phy_set_offsets_eth56g()
2177 rx_offset = cfg->rx_offset.no_fec; in ice_phy_set_offsets_eth56g()
2179 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); in ice_phy_set_offsets_eth56g()
2181 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); in ice_phy_set_offsets_eth56g()
2193 tx_offset = cfg->tx_offset.fc; in ice_phy_set_offsets_eth56g()
2195 tx_offset = cfg->tx_offset.rs; in ice_phy_set_offsets_eth56g()
2197 tx_offset = cfg->tx_offset.no_fec; in ice_phy_set_offsets_eth56g()
2198 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + in ice_phy_set_offsets_eth56g()
2199 cfg->tx_offset.onestep * onestep; in ice_phy_set_offsets_eth56g()
2206 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
2211 * * %0 - success
2212 * * %other - failed to write to PHY
2225 onestep = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_cfg_mac_eth56g()
2226 li = &hw->port_info->phy.link_info; in ice_phy_cfg_mac_eth56g()
2228 if (!!(li->an_info & ICE_AQ_FEC_EN)) { in ice_phy_cfg_mac_eth56g()
2232 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); in ice_phy_cfg_mac_eth56g()
2233 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); in ice_phy_cfg_mac_eth56g()
2247 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | in ice_phy_cfg_mac_eth56g()
2248 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | in ice_phy_cfg_mac_eth56g()
2250 cfg->tx_cw_dly.def + in ice_phy_cfg_mac_eth56g()
2251 onestep * cfg->tx_cw_dly.onestep) | in ice_phy_cfg_mac_eth56g()
2253 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | in ice_phy_cfg_mac_eth56g()
2255 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | in ice_phy_cfg_mac_eth56g()
2257 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | in ice_phy_cfg_mac_eth56g()
2258 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); in ice_phy_cfg_mac_eth56g()
2264 cfg->blktime); in ice_phy_cfg_mac_eth56g()
2275 val = cfg->mktime; in ice_phy_cfg_mac_eth56g()
2281 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
2290 * * %0 - success
2291 * * %other - PHY read/write failed
2314 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
2324 * * %0 - success
2325 * * %other - PHY read/write failed
2372 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
2384 * * %0 - success
2385 * * %-EBUSY- failed to acquire PTP semaphore
2386 * * %other - PHY read/write failed
2394 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); in ice_sync_phy_timer_eth56g()
2395 return -EBUSY; in ice_sync_phy_timer_eth56g()
2412 difference = phc_time - phy_time; in ice_sync_phy_timer_eth56g()
2425 /* Re-capture the timer values to flush the command registers and in ice_sync_phy_timer_eth56g()
2442 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2448 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2452 * * %0 - success
2453 * * %other - failed to write to PHY
2473 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2478 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2482 * * %0 - success
2483 * * %other - PHY read/write failed
2544 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
2563 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
2569 * * %0 - success
2570 * * %other - failed to initialize CGU
2580 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2588 * * %0 - success
2589 * * %other - failed to read from PHY
2593 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; in ice_ptp_read_tx_hwtstamp_status_eth56g()
2597 mask = (1 << hw->ptp.ports_per_phy) - 1; in ice_ptp_read_tx_hwtstamp_status_eth56g()
2600 for (phy = 0; phy < params->num_phys; phy++) { in ice_ptp_read_tx_hwtstamp_status_eth56g()
2607 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); in ice_ptp_read_tx_hwtstamp_status_eth56g()
2616 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2626 * * %0 - success
2627 * * %other - failed to read from PHY
2646 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C
2666 * ice_ptp_init_phy_e825c - initialize PHY parameters
2671 struct ice_ptp_hw *ptp = &hw->ptp; in ice_ptp_init_phy_e825c() local
2675 ptp->phy_model = ICE_PHY_ETH56G; in ice_ptp_init_phy_e825c()
2676 params = &ptp->phy.eth56g; in ice_ptp_init_phy_e825c()
2677 params->onestep_ena = false; in ice_ptp_init_phy_e825c()
2678 params->peer_delay = 0; in ice_ptp_init_phy_e825c()
2679 params->sfd_ena = false; in ice_ptp_init_phy_e825c()
2680 params->phy_addr[0] = eth56g_phy_0; in ice_ptp_init_phy_e825c()
2681 params->phy_addr[1] = eth56g_phy_1; in ice_ptp_init_phy_e825c()
2682 params->num_phys = 2; in ice_ptp_init_phy_e825c()
2683 ptp->ports_per_phy = 4; in ice_ptp_init_phy_e825c()
2684 ptp->num_lports = params->num_phys * ptp->ports_per_phy; in ice_ptp_init_phy_e825c()
2687 for (phy = 0; phy < params->num_phys; phy++) { in ice_ptp_init_phy_e825c()
2693 ptp->phy_model = ICE_PHY_UNSUP; in ice_ptp_init_phy_e825c()
2698 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw); in ice_ptp_init_phy_e825c()
2707 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2719 phy_port = port % hw->ptp.ports_per_phy; in ice_fill_phy_msg_e82x()
2720 phy = port / hw->ptp.ports_per_phy; in ice_fill_phy_msg_e82x()
2722 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); in ice_fill_phy_msg_e82x()
2725 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2726 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2728 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2729 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2733 msg->dest_dev = rmn_0; in ice_fill_phy_msg_e82x()
2735 msg->dest_dev = rmn_1; in ice_fill_phy_msg_e82x()
2737 msg->dest_dev = rmn_2; in ice_fill_phy_msg_e82x()
2741 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2794 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2839 * ice_read_phy_reg_e82x - Read a PHY register
2869 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2893 return -EINVAL; in ice_read_64b_phy_reg_e82x()
2916 * ice_write_phy_reg_e82x - Write a PHY register
2945 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
2967 return -EINVAL; in ice_write_40b_phy_reg_e82x()
2990 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
3014 return -EINVAL; in ice_write_64b_phy_reg_e82x()
3038 * ice_fill_quad_msg_e82x - Fill message data for quad register access
3048 * * %0 - OK
3049 * * %-EINVAL - invalid quad number
3057 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) in ice_fill_quad_msg_e82x()
3058 return -EINVAL; in ice_fill_quad_msg_e82x()
3060 msg->dest_dev = rmn_0; in ice_fill_quad_msg_e82x()
3062 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) in ice_fill_quad_msg_e82x()
3067 msg->msg_addr_low = lower_16_bits(addr); in ice_fill_quad_msg_e82x()
3068 msg->msg_addr_high = upper_16_bits(addr); in ice_fill_quad_msg_e82x()
3074 * ice_read_quad_reg_e82x - Read a PHY quad register
3108 * ice_write_quad_reg_e82x - Write a PHY quad register
3141 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
3163 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", in ice_read_phy_tstamp_e82x()
3170 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", in ice_read_phy_tstamp_e82x()
3185 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
3196 * to determine which timestamps are valid. Reading a timestamp auto-clears
3223 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
3237 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
3244 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) in ice_ptp_reset_ts_memory_e82x()
3249 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
3258 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_set_vernier_wl()
3274 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
3301 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
3322 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_time_e82x()
3348 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3358 * including the lower sub-nanosecond portion of the port timer.
3402 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3416 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_e82x()
3423 cycles = -(((s64)-adj) << 32); in ice_ptp_prep_phy_adj_e82x()
3425 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_adj_e82x()
3437 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3451 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_incval_e82x()
3468 * ice_ptp_read_port_capture - Read a port's local time capture
3509 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3520 * * %0 - success
3521 * * %other - failed to write to PHY
3557 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3560 * @link_out: if non-NULL, holds link speed on success
3561 * @fec_out: if non-NULL, holds FEC algorithm on success
3600 return -EIO; in ice_phy_get_speed_and_fec_e82x()
3620 return -EIO; in ice_phy_get_speed_and_fec_e82x()
3633 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3674 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3700 * -------+--------------+--------------+-------------
3759 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3768 * - Tx/Rx PAR/PCS markers
3771 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3774 * - Tx/Rx PAR/PCS markers
3775 * - Rx Deskew PAR/PCS markers
3778 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3779 * - Rx Deskew PAR/PCS markers
3780 * - Tx PAR/PCS markers
3788 * -------+-------+--------
3921 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
3952 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
3971 * Returns zero on success, -EBUSY if the hardware vernier offset
4001 return -EBUSY; in ice_phy_cfg_tx_offset_e82x()
4028 * multi-lane link speeds with RS-FEC. The lanes will always be in ice_phy_cfg_tx_offset_e82x()
4062 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
4113 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. in ice_phy_calc_pmd_adj_e82x()
4164 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx in ice_phy_calc_pmd_adj_e82x()
4174 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
4181 mult = (4 - rx_cycle) * 40; in ice_phy_calc_pmd_adj_e82x()
4196 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
4220 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
4251 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
4258 * well as adjusting for multi-lane alignment delay.
4274 * Returns zero on success, -EBUSY if the hardware vernier offset
4304 return -EBUSY; in ice_phy_cfg_rx_offset_e82x()
4323 /* For Rx, all multi-lane link speeds include a second Vernier in ice_phy_cfg_rx_offset_e82x()
4344 /* For RS-FEC, this adjustment adds delay, but for other modes, it in ice_phy_cfg_rx_offset_e82x()
4350 total_offset -= pmd; in ice_phy_cfg_rx_offset_e82x()
4372 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4384 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_clear_phy_offset_ready_e82x()
4406 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4463 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4480 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); in ice_sync_phy_timer_e82x()
4481 return -EBUSY; in ice_sync_phy_timer_e82x()
4496 difference = phc_time - phy_time; in ice_sync_phy_timer_e82x()
4512 /* Re-capture the timer values to flush the command registers and in ice_sync_phy_timer_e82x()
4534 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4540 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4584 * ice_start_phy_timer_e82x - Start the PHY clock timer
4589 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4681 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4716 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4747 * ice_ptp_init_phy_e82x - initialize PHY parameters
4748 * @ptp: pointer to the PTP HW struct
4750 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) in ice_ptp_init_phy_e82x() argument
4752 ptp->phy_model = ICE_PHY_E82X; in ice_ptp_init_phy_e82x()
4753 ptp->num_lports = 8; in ice_ptp_init_phy_e82x()
4754 ptp->ports_per_phy = 8; in ice_ptp_init_phy_e82x()
4764 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4794 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4823 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4844 for (i = TS_LL_READ_RETRIES; i > 0; i--) { in ice_read_phy_tstamp_ll_e810()
4861 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); in ice_read_phy_tstamp_ll_e810()
4862 return -EINVAL; in ice_read_phy_tstamp_ll_e810()
4866 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4887 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", in ice_read_phy_tstamp_sbq_e810()
4894 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", in ice_read_phy_tstamp_sbq_e810()
4906 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4922 if (hw->dev_caps.ts_dev_info.ts_ll_read) in ice_read_phy_tstamp_e810()
4939 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
4968 …ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %… in ice_clear_phy_tstamp_e810()
4975 …ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err … in ice_clear_phy_tstamp_e810()
4984 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
4987 * Perform E810-specific PTP hardware clock initialization steps.
4999 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phc_e810()
5003 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", in ice_ptp_init_phc_e810()
5010 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
5026 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_time_e810()
5045 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
5062 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_adj_e810()
5065 * nanoseconds. Sub-nanosecond adjustment is not supported. in ice_ptp_prep_phy_adj_e810()
5085 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
5099 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_incval_e810()
5121 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
5136 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
5163 * When found - the value will be cached in the hw structure and following calls
5175 if (hw->io_expander_handle) { in ice_get_pca9575_handle()
5176 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
5185 cmd->addr.topo_params.node_type_ctx = in ice_get_pca9575_handle()
5193 if (hw->device_id == ICE_DEV_ID_E810C_SFP) in ice_get_pca9575_handle()
5195 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) in ice_get_pca9575_handle()
5198 return -EOPNOTSUPP; in ice_get_pca9575_handle()
5200 cmd->addr.topo_params.index = idx; in ice_get_pca9575_handle()
5204 return -EOPNOTSUPP; in ice_get_pca9575_handle()
5209 return -EOPNOTSUPP; in ice_get_pca9575_handle()
5212 hw->io_expander_handle = in ice_get_pca9575_handle()
5214 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
5224 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
5225 * PCA9575 expander, so only bits 3-7 in data are valid.
5257 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5258 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5315 * ice_ptp_init_phy_e810 - initialize PHY parameters
5316 * @ptp: pointer to the PTP HW struct
5318 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) in ice_ptp_init_phy_e810() argument
5320 ptp->phy_model = ICE_PHY_E810; in ice_ptp_init_phy_e810()
5321 ptp->num_lports = 8; in ice_ptp_init_phy_e810()
5322 ptp->ports_per_phy = 4; in ice_ptp_init_phy_e810()
5333 * ice_ptp_lock - Acquire PTP global semaphore register lock
5336 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
5355 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); in ice_ptp_lock()
5370 * ice_ptp_unlock - Release PTP global semaphore register lock
5373 * Release the global PTP hardware semaphore lock. This is done by writing to
5378 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); in ice_ptp_unlock()
5382 * ice_ptp_init_hw - Initialize hw based on device type
5390 struct ice_ptp_hw *ptp = &hw->ptp; in ice_ptp_init_hw() local
5393 ice_ptp_init_phy_e82x(ptp); in ice_ptp_init_hw()
5395 ice_ptp_init_phy_e810(ptp); in ice_ptp_init_hw()
5399 ptp->phy_model = ICE_PHY_UNSUP; in ice_ptp_init_hw()
5403 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5410 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5413 * * %0 - success
5414 * %-EBUSY - PHY type not supported
5415 * * %other - failed to write port command
5420 switch (hw->ptp.phy_model) { in ice_ptp_write_port_cmd()
5426 return -EOPNOTSUPP; in ice_ptp_write_port_cmd()
5431 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5441 * * %0 - success
5442 * * %other - failed to write port command
5449 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_one_port_cmd()
5468 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5477 * * %0 - success
5478 * * %other - failed to write port command
5485 switch (hw->ptp.phy_model) { in ice_ptp_port_cmd()
5493 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_port_cmd()
5505 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5538 * ice_ptp_init_time - Initialize device time to provided value
5555 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_time()
5564 switch (hw->ptp.phy_model) { in ice_ptp_init_time()
5576 err = -EOPNOTSUPP; in ice_ptp_init_time()
5586 * ice_ptp_write_incval - Program PHC with new increment value
5590 * Program the PHC with a new increment value. This requires a three-step
5604 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_write_incval()
5610 switch (hw->ptp.phy_model) { in ice_ptp_write_incval()
5621 err = -EOPNOTSUPP; in ice_ptp_write_incval()
5631 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5635 * Program a new PHC incval while holding the PTP semaphore.
5642 return -EBUSY; in ice_ptp_write_incval_locked()
5652 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5657 * nanoseconds. This requires a three-step process:
5669 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_adj_clock()
5679 switch (hw->ptp.phy_model) { in ice_ptp_adj_clock()
5690 err = -EOPNOTSUPP; in ice_ptp_adj_clock()
5700 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5712 switch (hw->ptp.phy_model) { in ice_read_phy_tstamp()
5720 return -EOPNOTSUPP; in ice_read_phy_tstamp()
5725 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
5742 switch (hw->ptp.phy_model) { in ice_clear_phy_tstamp()
5750 return -EOPNOTSUPP; in ice_clear_phy_tstamp()
5755 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
5759 * * 0 - success
5760 * * negative - failure
5770 if (hw->mac_type != ICE_MAC_E810) in ice_get_pf_c827_idx()
5771 return -ENODEV; in ice_get_pf_c827_idx()
5773 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { in ice_get_pf_c827_idx()
5787 return -ENOENT; in ice_get_pf_c827_idx()
5794 return -EIO; in ice_get_pf_c827_idx()
5800 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
5805 switch (hw->ptp.phy_model) { in ice_ptp_reset_ts_memory()
5819 * ice_ptp_init_phc - Initialize PTP hardware clock
5822 * Perform the steps required to initialize the PTP hardware clock.
5826 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phc()
5834 switch (hw->ptp.phy_model) { in ice_ptp_init_phc()
5842 return -EOPNOTSUPP; in ice_ptp_init_phc()
5847 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
5859 switch (hw->ptp.phy_model) { in ice_get_phy_tx_tstamp_ready()
5871 return -EOPNOTSUPP; in ice_get_phy_tx_tstamp_ready()
5876 * ice_cgu_get_pin_desc_e823 - get pin description array
5888 if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
5897 } else if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
5915 * ice_cgu_get_pin_desc - get pin description array
5927 switch (hw->device_id) { in ice_cgu_get_pin_desc()
5966 * ice_cgu_get_num_pins - get pin description array size
5985 * ice_cgu_get_pin_type - get pin's type
6009 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
6037 * ice_cgu_get_pin_name - get pin's name
6063 * ice_get_cgu_state - get the state of the DPLL
6073 * This function will read the state of the DPLL(dpll_idx). Non-null
6095 /* current ref pin in dpll_state_refsel_status_X register */ in ice_get_cgu_state()
6107 * it would never return to FREERUN. This aligns to ITU-T G.781 in ice_get_cgu_state()
6129 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6138 * * 0 - success, information is valid
6139 * * negative - failure, information is not valid
6146 switch (hw->device_id) { in ice_get_cgu_rclk_pin_info()
6169 if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
6172 else if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
6176 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
6180 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
6188 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6194 * * 0 - success, state capabilities were modified
6195 * * negative - failure, capabilities were not modified
6202 switch (hw->device_id) { in ice_cgu_get_output_pin_state_caps()
6221 if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
6225 else if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
6231 return -EINVAL; in ice_cgu_get_output_pin_state_caps()