3197 	u32 oicr, ena_mask;  in ice_misc_intr()  local
3204 	oicr = rd32(hw, PFINT_OICR);  in ice_misc_intr()
3207 	if (oicr & PFINT_OICR_SWINT_M) {  in ice_misc_intr()
3212 	if (oicr & PFINT_OICR_MAL_DETECT_M) {  in ice_misc_intr()
3216 	if (oicr & PFINT_OICR_VFLR_M) {  in ice_misc_intr()
3229 	if (oicr & PFINT_OICR_GRST_M) {  in ice_misc_intr()
3274 	if (oicr & PFINT_OICR_TSYN_TX_M) {  in ice_misc_intr()
3294 	if (oicr & PFINT_OICR_TSYN_EVNT_M) {  in ice_misc_intr()
3312 	if (oicr & ICE_AUX_CRIT_ERR) {  in ice_misc_intr()
3313 		pf->oicr_err_reg |= oicr;  in ice_misc_intr()
3319 	oicr &= ena_mask;  in ice_misc_intr()
3320 	if (oicr) {  in ice_misc_intr()
3321 		dev_dbg(dev, "unhandled interrupt oicr=0x%08x\n", oicr);  in ice_misc_intr()
3325 		if (oicr & (PFINT_OICR_PCI_EXCEPTION_M |  in ice_misc_intr()