intel/ice/ice_hw_autogen.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
4 /* Machine-generated file */
19 #define PF_FW_ARQLEN_ARQVFE_M			BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M			BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M			BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M		BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M			BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M			BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M			BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M		BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M			BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M		BIT(31)
52 #define PF_MBX_ATQLEN_ATQCRIT_M			BIT(30)
53 #define PF_MBX_ATQLEN_ATQENABLE_M		BIT(31)
70 #define PF_SB_ARQLEN_ARQVFE_M			BIT(28)
72 #define PF_SB_ARQLEN_ARQOVFL_M			BIT(29)
74 #define PF_SB_ARQLEN_ARQCRIT_M			BIT(30)
76 #define PF_SB_ARQLEN_ARQENABLE_M		BIT(31)
93 #define PF_SB_ATQLEN_ATQVFE_M			BIT(28)
95 #define PF_SB_ATQLEN_ATQOVFL_M			BIT(29)
97 #define PF_SB_ATQLEN_ATQCRIT_M			BIT(30)
99 #define PF_SB_ATQLEN_ATQENABLE_M		BIT(31)
139 #define QRXFLXP_CNTXT_RXDID_PRIO_S		8
140 #define QRXFLXP_CNTXT_RXDID_PRIO_M		ICE_M(0x7, 8)
141 #define QRXFLXP_CNTXT_TS_M			BIT(11)
146 #define GLGEN_GPIO_CTL_PIN_DIR_M		BIT(4)
147 #define GLGEN_GPIO_CTL_PIN_FUNC_S		8
148 #define GLGEN_GPIO_CTL_PIN_FUNC_M		ICE_M(0xF, 8)
157 #define GLGEN_RTRIG_CORER_M			BIT(0)
158 #define GLGEN_RTRIG_GLOBR_M			BIT(1)
161 #define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M	BIT(2)
164 #define PFGEN_CTRL_PFSWR_M			BIT(0)
169 #define VPGEN_VFRSTAT_VFRD_M			BIT(0)
171 #define VPGEN_VFRTRIG_VFSWR_M			BIT(0)
173 #define GLINT_CTL_DIS_AUTOMASK_M		BIT(0)
185 #define GLINT_DYN_CTL_INTENA_M			BIT(0)
186 #define GLINT_DYN_CTL_CLEARPBA_M		BIT(1)
187 #define GLINT_DYN_CTL_SWINT_TRIG_M		BIT(2)
192 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M		BIT(24)
195 #define GLINT_DYN_CTL_WB_ON_ITR_M		BIT(30)
196 #define GLINT_DYN_CTL_INTENA_MSK_M		BIT(31)
199 #define GLINT_RATE_INTRL_ENA_M			BIT(6)
206 #define GLINT_VECT2FUNC_IS_PF_M			BIT(16)
213 #define PFINT_FW_CTL_CAUSE_ENA_M		BIT(30)
218 #define PFINT_MBX_CTL_CAUSE_ENA_M		BIT(30)
220 #define PFINT_OICR_TSYN_TX_M			BIT(11)
221 #define PFINT_OICR_TSYN_EVNT_M			BIT(12)
222 #define PFINT_OICR_ECC_ERR_M			BIT(16)
223 #define PFINT_OICR_MAL_DETECT_M			BIT(19)
224 #define PFINT_OICR_GRST_M			BIT(20)
225 #define PFINT_OICR_PCI_EXCEPTION_M		BIT(21)
226 #define PFINT_OICR_HMC_ERR_M			BIT(26)
227 #define PFINT_OICR_PE_PUSH_M			BIT(27)
228 #define PFINT_OICR_PE_CRITERR_M			BIT(28)
229 #define PFINT_OICR_VFLR_M			BIT(29)
230 #define PFINT_OICR_SWINT_M			BIT(31)
235 #define PFINT_OICR_CTL_CAUSE_ENA_M		BIT(30)
239 #define PFINT_SB_CTL_CAUSE_ENA_M		BIT(30)
246 #define QINT_RQCTL_CAUSE_ENA_M			BIT(30)
252 #define QINT_TQCTL_CAUSE_ENA_M			BIT(30)
258 #define VPINT_ALLOC_VALID_M			BIT(31)
264 #define VPINT_ALLOC_PCI_VALID_M			BIT(31)
266 #define VPINT_MBX_CTL_CAUSE_ENA_M		BIT(30)
272 #define QRX_CTRL_QENA_REQ_M			BIT(0)
274 #define QRX_CTRL_QENA_STAT_M			BIT(2)
286 #define VPLAN_RXQ_MAPENA_RX_ENA_M		BIT(0)
293 #define VPLAN_TXQ_MAPENA_TX_ENA_M		BIT(0)
295 #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX	8
300 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
310 #define GL_MDET_RX_VALID_M			BIT(31)
320 #define GL_MDET_TX_PQM_VALID_M			BIT(31)
322 	((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \
334 #define GL_MDET_TX_TCLAN_VALID_M		BIT(31)
336 #define PF_MDET_RX_VALID_M			BIT(0)
338 #define PF_MDET_TX_PQM_VALID_M			BIT(0)
340 	((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \
344 #define PF_MDET_TX_TCLAN_VALID_M		BIT(0)
346 #define VP_MDET_RX_VALID_M			BIT(0)
348 #define VP_MDET_TX_PQM_VALID_M			BIT(0)
350 #define VP_MDET_TX_TCLAN_VALID_M		BIT(0)
352 #define VP_MDET_TX_TDPU_VALID_M			BIT(0)
356 #define GL_MNG_FWSM_FW_LOADING_M		BIT(30)
358 #define GLNVM_FLA_LOCKED_M			BIT(6)
363 #define GLNVM_ULD_PCIER_DONE_M			BIT(0)
364 #define GLNVM_ULD_PCIER_DONE_1_M		BIT(1)
365 #define GLNVM_ULD_CORER_DONE_M			BIT(3)
366 #define GLNVM_ULD_GLOBR_DONE_M			BIT(4)
367 #define GLNVM_ULD_POR_DONE_M			BIT(5)
368 #define GLNVM_ULD_POR_DONE_1_M			BIT(8)
369 #define GLNVM_ULD_PCIER_DONE_2_M		BIT(9)
370 #define GLNVM_ULD_PE_DONE_M			BIT(10)
372 #define GLPCI_CNF2_CACHELINE_SIZE_M		BIT(1)
416 #define GLQF_HSYMM_ENABLE_BIT			BIT(7)
422 #define PFQF_FD_ENA_FD_ENA_M			BIT(0)
426 #define GLPRT_BPRCL(_i)				(0x00381380 + ((_i) * 8))
427 #define GLPRT_BPTCL(_i)				(0x00381240 + ((_i) * 8))
428 #define GLPRT_CRCERRS(_i)			(0x00380100 + ((_i) * 8))
429 #define GLPRT_GORCL(_i)				(0x00380000 + ((_i) * 8))
430 #define GLPRT_GOTCL(_i)				(0x00380B40 + ((_i) * 8))
431 #define GLPRT_ILLERRC(_i)			(0x003801C0 + ((_i) * 8))
432 #define GLPRT_LXOFFRXC(_i)			(0x003802C0 + ((_i) * 8))
433 #define GLPRT_LXOFFTXC(_i)			(0x00381180 + ((_i) * 8))
434 #define GLPRT_LXONRXC(_i)			(0x00380280 + ((_i) * 8))
435 #define GLPRT_LXONTXC(_i)			(0x00381140 + ((_i) * 8))
436 #define GLPRT_MLFC(_i)				(0x00380040 + ((_i) * 8))
437 #define GLPRT_MPRCL(_i)				(0x00381340 + ((_i) * 8))
438 #define GLPRT_MPTCL(_i)				(0x00381200 + ((_i) * 8))
439 #define GLPRT_MRFC(_i)				(0x00380080 + ((_i) * 8))
440 #define GLPRT_PRC1023L(_i)			(0x00380A00 + ((_i) * 8))
441 #define GLPRT_PRC127L(_i)			(0x00380940 + ((_i) * 8))
442 #define GLPRT_PRC1522L(_i)			(0x00380A40 + ((_i) * 8))
443 #define GLPRT_PRC255L(_i)			(0x00380980 + ((_i) * 8))
444 #define GLPRT_PRC511L(_i)			(0x003809C0 + ((_i) * 8))
445 #define GLPRT_PRC64L(_i)			(0x00380900 + ((_i) * 8))
446 #define GLPRT_PRC9522L(_i)			(0x00380A80 + ((_i) * 8))
447 #define GLPRT_PTC1023L(_i)			(0x00380C80 + ((_i) * 8))
448 #define GLPRT_PTC127L(_i)			(0x00380BC0 + ((_i) * 8))
449 #define GLPRT_PTC1522L(_i)			(0x00380CC0 + ((_i) * 8))
450 #define GLPRT_PTC255L(_i)			(0x00380C00 + ((_i) * 8))
451 #define GLPRT_PTC511L(_i)			(0x00380C40 + ((_i) * 8))
452 #define GLPRT_PTC64L(_i)			(0x00380B80 + ((_i) * 8))
453 #define GLPRT_PTC9522L(_i)			(0x00380D00 + ((_i) * 8))
454 #define GLPRT_PXOFFRXC(_i, _j)			(0x00380500 + ((_i) * 8 + (_j) * 64))
455 #define GLPRT_PXOFFTXC(_i, _j)			(0x00380F40 + ((_i) * 8 + (_j) * 64))
456 #define GLPRT_PXONRXC(_i, _j)			(0x00380300 + ((_i) * 8 + (_j) * 64))
457 #define GLPRT_PXONTXC(_i, _j)			(0x00380D40 + ((_i) * 8 + (_j) * 64))
458 #define GLPRT_RFC(_i)				(0x00380AC0 + ((_i) * 8))
459 #define GLPRT_RJC(_i)				(0x00380B00 + ((_i) * 8))
460 #define GLPRT_RLEC(_i)				(0x00380140 + ((_i) * 8))
461 #define GLPRT_ROC(_i)				(0x00380240 + ((_i) * 8))
462 #define GLPRT_RUC(_i)				(0x00380200 + ((_i) * 8))
463 #define GLPRT_RXON2OFFCNT(_i, _j)		(0x00380700 + ((_i) * 8 + (_j) * 64))
464 #define GLPRT_TDOLD(_i)				(0x00381280 + ((_i) * 8))
465 #define GLPRT_UPRCL(_i)				(0x00381300 + ((_i) * 8))
466 #define GLPRT_UPTCL(_i)				(0x003811C0 + ((_i) * 8))
467 #define GLSTAT_FD_CNT0L(_i)			(0x003A0000 + ((_i) * 8))
468 #define GLV_BPRCL(_i)				(0x003B6000 + ((_i) * 8))
469 #define GLV_BPTCL(_i)				(0x0030E000 + ((_i) * 8))
470 #define GLV_GORCL(_i)				(0x003B0000 + ((_i) * 8))
471 #define GLV_GOTCL(_i)				(0x00300000 + ((_i) * 8))
472 #define GLV_MPRCL(_i)				(0x003B4000 + ((_i) * 8))
473 #define GLV_MPTCL(_i)				(0x0030C000 + ((_i) * 8))
476 #define GLV_UPRCL(_i)				(0x003B2000 + ((_i) * 8))
477 #define GLV_UPTCL(_i)				(0x0030A000 + ((_i) * 8))
480 #define GLHH_ART_CTL_ACTIVE_M			BIT(0)
484 #define GLTSYN_AUX_IN_0_INT_ENA_M		BIT(4)
486 #define GLTSYN_AUX_OUT_0_OUT_ENA_M		BIT(0)
492 #define GLTSYN_ENA_TSYN_ENA_M			BIT(0)
505 #define GLTSYN_STAT_EVENT0_M			BIT(0)
506 #define GLTSYN_STAT_EVENT1_M			BIT(1)
507 #define GLTSYN_STAT_EVENT2_M			BIT(2)
515 #define PFHH_SEM_BUSY_M				BIT(0)
517 #define PFTSYN_SEM_BUSY_M			BIT(0)
528 #define PFPM_APM_APME_M				BIT(0)
530 #define PFPM_WUFC_MAG_M				BIT(1)
532 #define PFPM_WUS_LNKC_M				BIT(0)
533 #define PFPM_WUS_MAG_M				BIT(1)
534 #define PFPM_WUS_MNG_M				BIT(3)
535 #define PFPM_WUS_FW_RST_WK_M			BIT(31)
541 #define VFINT_DYN_CTLN_CLEARPBA_M		BIT(1)