Lines Matching +full:rclk +full:-
1 // SPDX-License-Identifier: GPL-2.0
16 * enum ice_dpll_pin_type - enumerate ice pin types:
32 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
40 * ice_dpll_is_reset - check if reset is in progress
47 * * false - no reset in progress
48 * * true - reset in progress
52 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
60 * ice_dpll_pin_freq_set - set pin's frequency
69 * Context: Called under pf->dplls.lock
71 * * 0 - success
72 * * negative - error on AQ or wrong pin type given
85 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
86 pin->flags[0], freq, 0); in ice_dpll_pin_freq_set()
90 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
94 return -EINVAL; in ice_dpll_pin_freq_set()
100 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
101 freq, pin->idx); in ice_dpll_pin_freq_set()
104 pin->freq = freq; in ice_dpll_pin_freq_set()
110 * ice_dpll_frequency_set - wrapper for pin callback for set frequency
121 * Context: Acquires pf->dplls.lock
123 * * 0 - success
124 * * negative - error pin not found or couldn't set in hw
135 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set()
139 return -EBUSY; in ice_dpll_frequency_set()
141 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
143 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
149 * ice_dpll_input_frequency_set - input pin callback for set frequency
159 * Context: Calls a function which acquires pf->dplls.lock
161 * * 0 - success
162 * * negative - error pin not found or couldn't set in hw
174 * ice_dpll_output_frequency_set - output pin callback for set frequency
184 * Context: Calls a function which acquires pf->dplls.lock
186 * * 0 - success
187 * * negative - error pin not found or couldn't set in hw
199 * ice_dpll_frequency_get - wrapper for pin callback for get frequency
210 * Context: Acquires pf->dplls.lock
212 * * 0 - success
213 * * negative - error pin not found or couldn't get from hw
223 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get()
225 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
226 *frequency = p->freq; in ice_dpll_frequency_get()
227 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
233 * ice_dpll_input_frequency_get - input pin callback for get frequency
243 * Context: Calls a function which acquires pf->dplls.lock
245 * * 0 - success
246 * * negative - error pin not found or couldn't get from hw
258 * ice_dpll_output_frequency_get - output pin callback for get frequency
268 * Context: Calls a function which acquires pf->dplls.lock
270 * * 0 - success
271 * * negative - error pin not found or couldn't get from hw
283 * ice_dpll_pin_enable - enable a pin on dplls
290 * Enable a pin on both dplls. Store current state in pin->flags.
292 * Context: Called under pf->dplls.lock
294 * * 0 - OK
295 * * negative - error
307 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_enable()
310 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_enable()
314 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_enable()
317 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, dpll_idx, in ice_dpll_pin_enable()
321 return -EINVAL; in ice_dpll_pin_enable()
326 ret, ice_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_enable()
327 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_enable()
333 * ice_dpll_pin_disable - disable a pin on dplls
339 * Disable a pin on both dplls. Store current state in pin->flags.
341 * Context: Called under pf->dplls.lock
343 * * 0 - OK
344 * * negative - error
356 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_disable()
358 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_disable()
361 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_disable()
363 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, 0, 0, 0); in ice_dpll_pin_disable()
366 return -EINVAL; in ice_dpll_pin_disable()
371 ret, ice_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_disable()
372 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_disable()
378 * ice_dpll_pin_state_update - update pin's state
386 * dpll, for rclk pins states are separated for each parent.
388 * Context: Called under pf->dplls.lock
390 * * 0 - OK
391 * * negative - error
403 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, in ice_dpll_pin_state_update()
404 NULL, NULL, &pin->flags[0], in ice_dpll_pin_state_update()
405 &pin->freq, &pin->phase_adjust); in ice_dpll_pin_state_update()
408 if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
409 if (pin->pin) { in ice_dpll_pin_state_update()
410 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
411 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
414 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
415 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
419 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
421 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
425 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
427 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
432 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
433 &pin->flags[0], &parent, in ice_dpll_pin_state_update()
434 &pin->freq, NULL); in ice_dpll_pin_state_update()
439 if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
440 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
441 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
444 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
445 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
449 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
451 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
456 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
460 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
462 &pin->flags[parent], in ice_dpll_pin_state_update()
467 pin->flags[parent]) in ice_dpll_pin_state_update()
468 pin->state[parent] = DPLL_PIN_STATE_CONNECTED; in ice_dpll_pin_state_update()
470 pin->state[parent] = in ice_dpll_pin_state_update()
475 return -EINVAL; in ice_dpll_pin_state_update()
484 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
485 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
490 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
491 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
496 * ice_dpll_hw_input_prio_set - set input priority value in hardware
505 * Context: Called under pf->dplls.lock
507 * * 0 - success
508 * * negative - failure
517 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
523 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
524 prio, pin->idx); in ice_dpll_hw_input_prio_set()
526 dpll->input_prio[pin->idx] = prio; in ice_dpll_hw_input_prio_set()
532 * ice_dpll_lock_status_get - get dpll lock status callback
541 * Context: Acquires pf->dplls.lock
543 * * 0 - success
544 * * negative - failure
553 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get()
555 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
556 *status = d->dpll_state; in ice_dpll_lock_status_get()
557 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
563 * ice_dpll_mode_get - get dpll's working mode
571 * Context: Acquires pf->dplls.lock
573 * * 0 - success
574 * * negative - failure
581 struct ice_pf *pf = d->pf; in ice_dpll_mode_get()
583 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
584 *mode = d->mode; in ice_dpll_mode_get()
585 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
591 * ice_dpll_pin_state_set - set pin's state on dpll
602 * Context: Acquires pf->dplls.lock
604 * * 0 - OK or no change required
605 * * negative - error
615 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set()
619 return -EBUSY; in ice_dpll_pin_state_set()
621 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
623 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
626 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
629 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
635 * ice_dpll_output_state_set - enable/disable output pin on dpll device
645 * Context: Calls a function which acquires pf->dplls.lock
647 * * 0 - successfully enabled mode
648 * * negative - failed to enable mode
661 return -EINVAL; in ice_dpll_output_state_set()
662 if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED) in ice_dpll_output_state_set()
670 * ice_dpll_input_state_set - enable/disable input pin on dpll levice
680 * Context: Calls a function which acquires pf->dplls.lock
682 * * 0 - successfully enabled mode
683 * * negative - failed to enable mode
698 * ice_dpll_pin_state_get - set pin's state on dpll
709 * Context: Acquires pf->dplls.lock
711 * * 0 - success
712 * * negative - failed to get state
723 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get()
727 return -EBUSY; in ice_dpll_pin_state_get()
729 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
735 *state = p->state[d->dpll_idx]; in ice_dpll_pin_state_get()
738 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
744 * ice_dpll_output_state_get - get output pin state on dpll device
754 * Context: Calls a function which acquires pf->dplls.lock
756 * * 0 - success
757 * * negative - failed to get state
770 * ice_dpll_input_state_get - get input pin state on dpll device
780 * Context: Calls a function which acquires pf->dplls.lock
782 * * 0 - success
783 * * negative - failed to get state
796 * ice_dpll_input_prio_get - get dpll's input prio
801 * @prio: on success - returns input priority on dpll
806 * Context: Acquires pf->dplls.lock
808 * * 0 - success
809 * * negative - failure
818 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get()
820 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
821 *prio = d->input_prio[p->idx]; in ice_dpll_input_prio_get()
822 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
828 * ice_dpll_input_prio_set - set dpll input prio
838 * Context: Acquires pf->dplls.lock
840 * * 0 - success
841 * * negative - failure
850 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set()
854 return -EBUSY; in ice_dpll_input_prio_set()
856 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
858 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
864 * ice_dpll_input_direction - callback for get input pin direction
875 * * 0 - success
889 * ice_dpll_output_direction - callback for get output pin direction
900 * * 0 - success
914 * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
924 * Context: Acquires pf->dplls.lock
926 * * 0 - success
927 * * negative - error
936 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get()
938 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
939 *phase_adjust = p->phase_adjust; in ice_dpll_pin_phase_adjust_get()
940 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
946 * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
958 * Context: Acquires pf->dplls.lock
960 * * 0 - success
961 * * negative - error
972 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set()
977 return -EBUSY; in ice_dpll_pin_phase_adjust_set()
979 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
983 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
985 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_pin_phase_adjust_set()
987 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
992 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) in ice_dpll_pin_phase_adjust_set()
994 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
996 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
1000 ret = -EINVAL; in ice_dpll_pin_phase_adjust_set()
1003 p->phase_adjust = phase_adjust; in ice_dpll_pin_phase_adjust_set()
1004 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1009 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1010 phase_adjust, p->idx, d->dpll_idx); in ice_dpll_pin_phase_adjust_set()
1016 * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
1027 * Context: Calls a function which acquires pf->dplls.lock
1029 * * 0 - success
1030 * * negative - error
1044 * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
1055 * Context: Calls a function which acquires pf->dplls.lock
1057 * * 0 - success
1058 * * negative - error
1075 * ice_dpll_phase_offset_get - callback for get dpll phase shift value
1086 * Context: Acquires pf->dplls.lock
1088 * * 0 - success
1089 * * negative - error
1097 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get()
1099 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1100 if (d->active_input == pin) in ice_dpll_phase_offset_get()
1101 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1104 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1110 * ice_dpll_output_esync_set - callback for setting embedded sync
1121 * Context: Acquires pf->dplls.lock
1123 * * 0 - success
1124 * * negative - error
1133 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_set()
1138 return -EBUSY; in ice_dpll_output_esync_set()
1139 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1140 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) in ice_dpll_output_esync_set()
1143 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { in ice_dpll_output_esync_set()
1147 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1151 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) { in ice_dpll_output_esync_set()
1155 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1159 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1165 * ice_dpll_output_esync_get - callback for getting embedded sync config
1176 * Context: Acquires pf->dplls.lock
1178 * * 0 - success
1179 * * negative - error
1189 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_get()
1192 return -EBUSY; in ice_dpll_output_esync_get()
1193 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1194 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) || in ice_dpll_output_esync_get()
1195 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { in ice_dpll_output_esync_get()
1196 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1197 return -EOPNOTSUPP; in ice_dpll_output_esync_get()
1199 esync->range = ice_esync_range; in ice_dpll_output_esync_get()
1200 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_output_esync_get()
1201 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { in ice_dpll_output_esync_get()
1202 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_output_esync_get()
1203 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_output_esync_get()
1205 esync->freq = 0; in ice_dpll_output_esync_get()
1206 esync->pulse = 0; in ice_dpll_output_esync_get()
1208 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1214 * ice_dpll_input_esync_set - callback for setting embedded sync
1225 * Context: Acquires pf->dplls.lock
1227 * * 0 - success
1228 * * negative - error
1237 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_set()
1242 return -EBUSY; in ice_dpll_input_esync_set()
1243 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1244 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_input_esync_set()
1247 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { in ice_dpll_input_esync_set()
1251 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1255 if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) { in ice_dpll_input_esync_set()
1259 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1263 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1269 * ice_dpll_input_esync_get - callback for getting embedded sync config
1280 * Context: Acquires pf->dplls.lock
1282 * * 0 - success
1283 * * negative - error
1293 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_get()
1296 return -EBUSY; in ice_dpll_input_esync_get()
1297 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1298 if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) || in ice_dpll_input_esync_get()
1299 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { in ice_dpll_input_esync_get()
1300 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1301 return -EOPNOTSUPP; in ice_dpll_input_esync_get()
1303 esync->range = ice_esync_range; in ice_dpll_input_esync_get()
1304 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_input_esync_get()
1305 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { in ice_dpll_input_esync_get()
1306 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_input_esync_get()
1307 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_input_esync_get()
1309 esync->freq = 0; in ice_dpll_input_esync_get()
1310 esync->pulse = 0; in ice_dpll_input_esync_get()
1312 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1318 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
1326 * Dpll subsystem callback, set a state of a rclk pin on a parent pin
1328 * Context: Acquires pf->dplls.lock
1330 * * 0 - success
1331 * * negative - failure
1342 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set()
1343 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_set()
1347 return -EBUSY; in ice_dpll_rclk_state_on_pin_set()
1349 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1350 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
1351 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
1354 if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) || in ice_dpll_rclk_state_on_pin_set()
1355 (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) { in ice_dpll_rclk_state_on_pin_set()
1358 p->idx, state, parent->idx); in ice_dpll_rclk_state_on_pin_set()
1361 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
1362 &p->freq); in ice_dpll_rclk_state_on_pin_set()
1367 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
1368 state, p->idx, parent->idx); in ice_dpll_rclk_state_on_pin_set()
1370 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1376 * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin
1386 * Context: Acquires pf->dplls.lock
1388 * * 0 - success
1389 * * negative - failure
1399 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get()
1400 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_get()
1404 return -EBUSY; in ice_dpll_rclk_state_on_pin_get()
1406 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1407 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
1408 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
1416 *state = p->state[hw_idx]; in ice_dpll_rclk_state_on_pin_get()
1419 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1463 * ice_generate_clock_id - generates unique clock_id for registering dpll.
1473 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
1477 * ice_dpll_notify_changes - notify dpll subsystem about changes
1486 if (d->prev_dpll_state != d->dpll_state) { in ice_dpll_notify_changes()
1487 d->prev_dpll_state = d->dpll_state; in ice_dpll_notify_changes()
1488 dpll_device_change_ntf(d->dpll); in ice_dpll_notify_changes()
1490 if (d->prev_input != d->active_input) { in ice_dpll_notify_changes()
1491 if (d->prev_input) in ice_dpll_notify_changes()
1492 dpll_pin_change_ntf(d->prev_input); in ice_dpll_notify_changes()
1493 d->prev_input = d->active_input; in ice_dpll_notify_changes()
1494 if (d->active_input) { in ice_dpll_notify_changes()
1495 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
1499 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
1500 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
1501 if (!pin_notified && d->active_input) in ice_dpll_notify_changes()
1502 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
1507 * ice_dpll_update_state - update dpll state
1514 * Context: Called by kworker under pf->dplls.lock
1516 * * 0 - success
1517 * * negative - AQ failure
1525 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
1526 &d->input_idx, &d->ref_state, &d->eec_mode, in ice_dpll_update_state()
1527 &d->phase_offset, &d->dpll_state); in ice_dpll_update_state()
1531 d->dpll_idx, d->prev_input_idx, d->input_idx, in ice_dpll_update_state()
1532 d->dpll_state, d->prev_dpll_state, d->mode); in ice_dpll_update_state()
1536 d->dpll_idx, ret, in ice_dpll_update_state()
1537 ice_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
1541 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED || in ice_dpll_update_state()
1542 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ) in ice_dpll_update_state()
1543 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
1544 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1548 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER || in ice_dpll_update_state()
1549 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) { in ice_dpll_update_state()
1550 d->active_input = NULL; in ice_dpll_update_state()
1551 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) in ice_dpll_update_state()
1552 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1553 d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
1554 d->input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
1559 } else if (d->input_idx != d->prev_input_idx) { in ice_dpll_update_state()
1560 if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
1561 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
1566 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
1567 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1568 d->active_input = p->pin; in ice_dpll_update_state()
1573 d->prev_input_idx = d->input_idx; in ice_dpll_update_state()
1580 * ice_dpll_periodic_work - DPLLs periodic worker
1584 * Context: Holds pf->dplls.lock
1590 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
1591 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
1594 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
1596 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
1601 d->cgu_state_acq_err_num++; in ice_dpll_periodic_work()
1603 if (d->cgu_state_acq_err_num > in ice_dpll_periodic_work()
1607 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1611 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1617 kthread_queue_delayed_work(d->kworker, &d->work, in ice_dpll_periodic_work()
1623 * ice_dpll_release_pins - release pins resources from dpll subsystem
1638 * ice_dpll_get_pins - get pins from dpll subsystem
1645 * Get pins - allocate - in dpll subsystem, store them in pin field of given
1649 * * 0 - success
1650 * * negative - allocation failure reason
1670 while (--i >= 0) in ice_dpll_get_pins()
1676 * ice_dpll_unregister_pins - unregister pins from a dpll
1696 * ice_dpll_register_pins - register pins with a dpll
1705 * * 0 - success
1706 * * negative - registration failure reason
1723 while (--i >= 0) in ice_dpll_register_pins()
1729 * ice_dpll_deinit_direct_pins - deinitialize direct pins
1754 * ice_dpll_init_direct_pins - initialize direct pins
1768 * * 0 - success
1769 * * negative - registration failure reason
1779 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
1801 * ice_dpll_deinit_rclk_pin - release rclk pin resources
1804 * Deregister rclk pin from parent pins and release resources in dpll subsystem.
1808 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin() local
1813 for (i = 0; i < rclk->num_parents; i++) { in ice_dpll_deinit_rclk_pin()
1814 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
1817 dpll_pin_on_pin_unregister(parent, rclk->pin, in ice_dpll_deinit_rclk_pin()
1818 &ice_dpll_rclk_ops, rclk); in ice_dpll_deinit_rclk_pin()
1820 if (WARN_ON_ONCE(!vsi || !vsi->netdev)) in ice_dpll_deinit_rclk_pin()
1822 dpll_netdev_pin_clear(vsi->netdev); in ice_dpll_deinit_rclk_pin()
1823 dpll_pin_put(rclk->pin); in ice_dpll_deinit_rclk_pin()
1827 * ice_dpll_init_rclk_pins - initialize recovered clock pin
1838 * * 0 - success
1839 * * negative - registration failure reason
1849 if (WARN_ON((!vsi || !vsi->netdev))) in ice_dpll_init_rclk_pins()
1850 return -EINVAL; in ice_dpll_init_rclk_pins()
1852 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
1855 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
1856 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
1858 ret = -ENODEV; in ice_dpll_init_rclk_pins()
1861 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1862 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1866 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
1872 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
1873 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1874 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1881 * ice_dpll_deinit_pins - deinitialize direct pins
1890 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
1891 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
1892 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
1893 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
1894 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
1895 struct ice_dpll *de = &d->eec; in ice_dpll_deinit_pins()
1896 struct ice_dpll *dp = &d->pps; in ice_dpll_deinit_pins()
1900 ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
1902 ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
1907 ice_dpll_unregister_pins(dp->dpll, outputs, in ice_dpll_deinit_pins()
1909 ice_dpll_unregister_pins(de->dpll, outputs, in ice_dpll_deinit_pins()
1916 * ice_dpll_init_pins - init pins and register pins with a dplls
1924 * * 0 - success
1925 * * negative - initialization failure reason
1932 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
1933 pf->dplls.num_inputs, in ice_dpll_init_pins()
1935 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
1939 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1940 pf->dplls.num_inputs, in ice_dpll_init_pins()
1941 pf->dplls.num_outputs, in ice_dpll_init_pins()
1943 pf->dplls.eec.dpll, in ice_dpll_init_pins()
1944 pf->dplls.pps.dpll); in ice_dpll_init_pins()
1948 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id; in ice_dpll_init_pins()
1949 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx, in ice_dpll_init_pins()
1956 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1957 pf->dplls.num_outputs, in ice_dpll_init_pins()
1958 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1959 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1961 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
1962 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1963 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1968 * ice_dpll_deinit_dpll - deinitialize dpll device
1980 dpll_device_unregister(d->dpll, &ice_dpll_ops, d); in ice_dpll_deinit_dpll()
1981 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll()
1985 * ice_dpll_init_dpll - initialize dpll device in dpll subsystem
1995 * * 0 - success
1996 * * negative - initialization failure reason
2002 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
2005 d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE); in ice_dpll_init_dpll()
2006 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll()
2007 ret = PTR_ERR(d->dpll); in ice_dpll_init_dpll()
2012 d->pf = pf; in ice_dpll_init_dpll()
2015 ret = dpll_device_register(d->dpll, type, &ice_dpll_ops, d); in ice_dpll_init_dpll()
2017 dpll_device_put(d->dpll); in ice_dpll_init_dpll()
2026 * ice_dpll_deinit_worker - deinitialize dpll kworker
2033 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
2035 kthread_cancel_delayed_work_sync(&d->work); in ice_dpll_deinit_worker()
2036 kthread_destroy_worker(d->kworker); in ice_dpll_deinit_worker()
2040 * ice_dpll_init_worker - Initialize DPLLs periodic worker
2045 * Context: Shall be called after pf->dplls.lock is initialized.
2047 * * 0 - success
2048 * * negative - create worker failure
2052 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
2055 kthread_init_delayed_work(&d->work, ice_dpll_periodic_work); in ice_dpll_init_worker()
2056 kworker = kthread_create_worker(0, "ice-dplls-%s", in ice_dpll_init_worker()
2060 d->kworker = kworker; in ice_dpll_init_worker()
2061 d->cgu_state_acq_err_num = 0; in ice_dpll_init_worker()
2062 kthread_queue_delayed_work(d->kworker, &d->work, 0); in ice_dpll_init_worker()
2068 * ice_dpll_init_info_pins_generic - initializes generic pins info
2075 * * 0 - success
2076 * * negative - init failure reason
2080 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_pins_generic()
2086 int i, pin_num, ret = -EINVAL; in ice_dpll_init_info_pins_generic()
2091 pin_num = pf->dplls.num_inputs; in ice_dpll_init_info_pins_generic()
2092 pins = pf->dplls.inputs; in ice_dpll_init_info_pins_generic()
2093 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_pins_generic()
2097 pin_num = pf->dplls.num_outputs; in ice_dpll_init_info_pins_generic()
2098 pins = pf->dplls.outputs; in ice_dpll_init_info_pins_generic()
2099 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_pins_generic()
2109 pins[i].prop.phase_range.max = -phase_adj_max; in ice_dpll_init_info_pins_generic()
2121 ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i, in ice_dpll_init_info_pins_generic()
2122 &de->input_prio[i]); in ice_dpll_init_info_pins_generic()
2125 ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i, in ice_dpll_init_info_pins_generic()
2126 &dp->input_prio[i]); in ice_dpll_init_info_pins_generic()
2135 * ice_dpll_init_info_direct_pins - initializes direct pins info
2143 * * 0 - success
2144 * * negative - init failure reason
2150 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
2151 int num_pins, i, ret = -EINVAL; in ice_dpll_init_info_direct_pins()
2152 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
2160 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
2161 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
2165 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
2166 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
2170 return -EINVAL; in ice_dpll_init_info_direct_pins()
2181 ret = ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i, in ice_dpll_init_info_direct_pins()
2182 &de->input_prio[i]); in ice_dpll_init_info_direct_pins()
2185 ret = ice_aq_get_cgu_ref_prio(hw, dp->dpll_idx, i, in ice_dpll_init_info_direct_pins()
2186 &dp->input_prio[i]); in ice_dpll_init_info_direct_pins()
2192 pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
2194 -pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
2197 pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
2199 -pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
2218 * ice_dpll_init_info_rclk_pin - initializes rclk pin information
2221 * Init information for rclk pin, cache them in pf->dplls.rclk.
2224 * * 0 - success
2225 * * negative - init failure reason
2229 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
2231 pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT; in ice_dpll_init_info_rclk_pin()
2232 pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; in ice_dpll_init_info_rclk_pin()
2233 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
2240 * ice_dpll_init_pins_info - init pins info wrapper
2247 * * 0 - success
2248 * * negative - init failure reason
2260 return -EINVAL; in ice_dpll_init_pins_info()
2265 * ice_dpll_deinit_info - release memory allocated for pins info
2272 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
2273 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
2274 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
2275 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
2279 * ice_dpll_init_info - prepare pf's dpll information structure
2283 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
2286 * * 0 - success
2287 * * negative - init failure reason
2292 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
2293 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
2294 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
2295 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
2298 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
2303 ret, ice_aq_str(hw->adminq.sq_last_status)); in ice_dpll_init_info()
2307 de->dpll_idx = abilities.eec_dpll_idx; in ice_dpll_init_info()
2308 dp->dpll_idx = abilities.pps_dpll_idx; in ice_dpll_init_info()
2309 d->num_inputs = abilities.num_inputs; in ice_dpll_init_info()
2310 d->num_outputs = abilities.num_outputs; in ice_dpll_init_info()
2311 d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj); in ice_dpll_init_info()
2312 d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj); in ice_dpll_init_info()
2314 alloc_size = sizeof(*d->inputs) * d->num_inputs; in ice_dpll_init_info()
2315 d->inputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2316 if (!d->inputs) in ice_dpll_init_info()
2317 return -ENOMEM; in ice_dpll_init_info()
2319 alloc_size = sizeof(*de->input_prio) * d->num_inputs; in ice_dpll_init_info()
2320 de->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2321 if (!de->input_prio) in ice_dpll_init_info()
2322 return -ENOMEM; in ice_dpll_init_info()
2324 dp->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2325 if (!dp->input_prio) in ice_dpll_init_info()
2326 return -ENOMEM; in ice_dpll_init_info()
2333 alloc_size = sizeof(*d->outputs) * d->num_outputs; in ice_dpll_init_info()
2334 d->outputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2335 if (!d->outputs) { in ice_dpll_init_info()
2336 ret = -ENOMEM; in ice_dpll_init_info()
2345 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
2346 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
2349 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
2350 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
2354 de->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
2355 dp->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
2358 "%s - success, inputs:%u, outputs:%u rclk-parents:%u\n", in ice_dpll_init_info()
2359 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); in ice_dpll_init_info()
2365 "%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n", in ice_dpll_init_info()
2366 __func__, d->inputs, de->input_prio, in ice_dpll_init_info()
2367 dp->input_prio, d->outputs); in ice_dpll_init_info()
2373 * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem
2381 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2387 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
2392 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
2393 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
2395 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
2399 * ice_dpll_init - initialize support for dpll subsystem
2406 * Context: Initializes pf->dplls.lock mutex.
2411 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
2414 mutex_init(&d->lock); in ice_dpll_init()
2418 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
2421 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
2432 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
2439 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
2441 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
2445 mutex_destroy(&d->lock); in ice_dpll_init()