Lines Matching full:hw
9 static void i40e_resume_aq(struct i40e_hw *hw);
13 * @hw: pointer to the hardware structure
15 static int i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_asq_ring() argument
19 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, in i40e_alloc_adminq_asq_ring()
20 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
26 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, in i40e_alloc_adminq_asq_ring()
27 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
30 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_alloc_adminq_asq_ring()
39 * @hw: pointer to the hardware structure
41 static int i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_arq_ring() argument
45 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, in i40e_alloc_adminq_arq_ring()
46 (hw->aq.num_arq_entries * in i40e_alloc_adminq_arq_ring()
55 * @hw: pointer to the hardware structure
60 static void i40e_free_adminq_asq(struct i40e_hw *hw) in i40e_free_adminq_asq() argument
62 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_adminq_asq()
67 * @hw: pointer to the hardware structure
72 static void i40e_free_adminq_arq(struct i40e_hw *hw) in i40e_free_adminq_arq() argument
74 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_adminq_arq()
79 * @hw: pointer to the hardware structure
81 static int i40e_alloc_arq_bufs(struct i40e_hw *hw) in i40e_alloc_arq_bufs() argument
93 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, in i40e_alloc_arq_bufs()
94 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_arq_bufs()
97 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; in i40e_alloc_arq_bufs()
100 for (i = 0; i < hw->aq.num_arq_entries; i++) { in i40e_alloc_arq_bufs()
101 bi = &hw->aq.arq.r.arq_bi[i]; in i40e_alloc_arq_bufs()
102 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_arq_bufs()
103 hw->aq.arq_buf_size, in i40e_alloc_arq_bufs()
109 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); in i40e_alloc_arq_bufs()
112 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_alloc_arq_bufs()
137 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_alloc_arq_bufs()
138 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_alloc_arq_bufs()
145 * @hw: pointer to the hardware structure
147 static int i40e_alloc_asq_bufs(struct i40e_hw *hw) in i40e_alloc_asq_bufs() argument
154 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, in i40e_alloc_asq_bufs()
155 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_asq_bufs()
158 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; in i40e_alloc_asq_bufs()
161 for (i = 0; i < hw->aq.num_asq_entries; i++) { in i40e_alloc_asq_bufs()
162 bi = &hw->aq.asq.r.asq_bi[i]; in i40e_alloc_asq_bufs()
163 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_asq_bufs()
164 hw->aq.asq_buf_size, in i40e_alloc_asq_bufs()
176 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_alloc_asq_bufs()
177 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_alloc_asq_bufs()
184 * @hw: pointer to the hardware structure
186 static void i40e_free_arq_bufs(struct i40e_hw *hw) in i40e_free_arq_bufs() argument
191 for (i = 0; i < hw->aq.num_arq_entries; i++) in i40e_free_arq_bufs()
192 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_free_arq_bufs()
195 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_arq_bufs()
198 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_free_arq_bufs()
203 * @hw: pointer to the hardware structure
205 static void i40e_free_asq_bufs(struct i40e_hw *hw) in i40e_free_asq_bufs() argument
210 for (i = 0; i < hw->aq.num_asq_entries; i++) in i40e_free_asq_bufs()
211 if (hw->aq.asq.r.asq_bi[i].pa) in i40e_free_asq_bufs()
212 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_free_asq_bufs()
215 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); in i40e_free_asq_bufs()
218 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_asq_bufs()
221 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_free_asq_bufs()
226 * @hw: pointer to the hardware structure
230 static int i40e_config_asq_regs(struct i40e_hw *hw) in i40e_config_asq_regs() argument
236 wr32(hw, I40E_PF_ATQH, 0); in i40e_config_asq_regs()
237 wr32(hw, I40E_PF_ATQT, 0); in i40e_config_asq_regs()
240 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
242 wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
243 wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
246 reg = rd32(hw, I40E_PF_ATQBAL); in i40e_config_asq_regs()
247 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) in i40e_config_asq_regs()
255 * @hw: pointer to the hardware structure
259 static int i40e_config_arq_regs(struct i40e_hw *hw) in i40e_config_arq_regs() argument
265 wr32(hw, I40E_PF_ARQH, 0); in i40e_config_arq_regs()
266 wr32(hw, I40E_PF_ARQT, 0); in i40e_config_arq_regs()
269 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
271 wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
272 wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
274 /* Update tail in the HW to post pre-allocated buffers */ in i40e_config_arq_regs()
275 wr32(hw, I40E_PF_ARQT, hw->aq.num_arq_entries - 1); in i40e_config_arq_regs()
278 reg = rd32(hw, I40E_PF_ARQBAL); in i40e_config_arq_regs()
279 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) in i40e_config_arq_regs()
287 * @hw: pointer to the hardware structure
291 * in the hw->aq structure:
292 * - hw->aq.num_asq_entries
293 * - hw->aq.arq_buf_size
298 static int i40e_init_asq(struct i40e_hw *hw) in i40e_init_asq() argument
302 if (hw->aq.asq.count > 0) { in i40e_init_asq()
309 if ((hw->aq.num_asq_entries == 0) || in i40e_init_asq()
310 (hw->aq.asq_buf_size == 0)) { in i40e_init_asq()
315 hw->aq.asq.next_to_use = 0; in i40e_init_asq()
316 hw->aq.asq.next_to_clean = 0; in i40e_init_asq()
319 ret_code = i40e_alloc_adminq_asq_ring(hw); in i40e_init_asq()
324 ret_code = i40e_alloc_asq_bufs(hw); in i40e_init_asq()
329 ret_code = i40e_config_asq_regs(hw); in i40e_init_asq()
334 hw->aq.asq.count = hw->aq.num_asq_entries; in i40e_init_asq()
338 i40e_free_adminq_asq(hw); in i40e_init_asq()
346 * @hw: pointer to the hardware structure
350 * in the hw->aq structure:
351 * - hw->aq.num_asq_entries
352 * - hw->aq.arq_buf_size
357 static int i40e_init_arq(struct i40e_hw *hw) in i40e_init_arq() argument
361 if (hw->aq.arq.count > 0) { in i40e_init_arq()
368 if ((hw->aq.num_arq_entries == 0) || in i40e_init_arq()
369 (hw->aq.arq_buf_size == 0)) { in i40e_init_arq()
374 hw->aq.arq.next_to_use = 0; in i40e_init_arq()
375 hw->aq.arq.next_to_clean = 0; in i40e_init_arq()
378 ret_code = i40e_alloc_adminq_arq_ring(hw); in i40e_init_arq()
383 ret_code = i40e_alloc_arq_bufs(hw); in i40e_init_arq()
388 ret_code = i40e_config_arq_regs(hw); in i40e_init_arq()
393 hw->aq.arq.count = hw->aq.num_arq_entries; in i40e_init_arq()
397 i40e_free_adminq_arq(hw); in i40e_init_arq()
405 * @hw: pointer to the hardware structure
409 static int i40e_shutdown_asq(struct i40e_hw *hw) in i40e_shutdown_asq() argument
413 mutex_lock(&hw->aq.asq_mutex); in i40e_shutdown_asq()
415 if (hw->aq.asq.count == 0) { in i40e_shutdown_asq()
421 wr32(hw, I40E_PF_ATQH, 0); in i40e_shutdown_asq()
422 wr32(hw, I40E_PF_ATQT, 0); in i40e_shutdown_asq()
423 wr32(hw, I40E_PF_ATQLEN, 0); in i40e_shutdown_asq()
424 wr32(hw, I40E_PF_ATQBAL, 0); in i40e_shutdown_asq()
425 wr32(hw, I40E_PF_ATQBAH, 0); in i40e_shutdown_asq()
427 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_asq()
430 i40e_free_asq_bufs(hw); in i40e_shutdown_asq()
433 mutex_unlock(&hw->aq.asq_mutex); in i40e_shutdown_asq()
439 * @hw: pointer to the hardware structure
443 static int i40e_shutdown_arq(struct i40e_hw *hw) in i40e_shutdown_arq() argument
447 mutex_lock(&hw->aq.arq_mutex); in i40e_shutdown_arq()
449 if (hw->aq.arq.count == 0) { in i40e_shutdown_arq()
455 wr32(hw, I40E_PF_ARQH, 0); in i40e_shutdown_arq()
456 wr32(hw, I40E_PF_ARQT, 0); in i40e_shutdown_arq()
457 wr32(hw, I40E_PF_ARQLEN, 0); in i40e_shutdown_arq()
458 wr32(hw, I40E_PF_ARQBAL, 0); in i40e_shutdown_arq()
459 wr32(hw, I40E_PF_ARQBAH, 0); in i40e_shutdown_arq()
461 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_arq()
464 i40e_free_arq_bufs(hw); in i40e_shutdown_arq()
467 mutex_unlock(&hw->aq.arq_mutex); in i40e_shutdown_arq()
472 * i40e_set_hw_caps - set HW flags
473 * @hw: pointer to the hardware structure
475 static void i40e_set_hw_caps(struct i40e_hw *hw) in i40e_set_hw_caps() argument
477 bitmap_zero(hw->caps, I40E_HW_CAPS_NBITS); in i40e_set_hw_caps()
479 switch (hw->mac.type) { in i40e_set_hw_caps()
481 if (i40e_is_aq_api_ver_ge(hw, 1, in i40e_set_hw_caps()
483 set_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps); in i40e_set_hw_caps()
484 set_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps); in i40e_set_hw_caps()
486 set_bit(I40E_HW_CAP_802_1AD, hw->caps); in i40e_set_hw_caps()
488 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) { in i40e_set_hw_caps()
490 set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, hw->caps); in i40e_set_hw_caps()
492 if (i40e_is_fw_ver_lt(hw, 4, 33)) { in i40e_set_hw_caps()
493 set_bit(I40E_HW_CAP_RESTART_AUTONEG, hw->caps); in i40e_set_hw_caps()
495 set_bit(I40E_HW_CAP_NO_DCB_SUPPORT, hw->caps); in i40e_set_hw_caps()
497 if (i40e_is_fw_ver_lt(hw, 4, 3)) { in i40e_set_hw_caps()
499 set_bit(I40E_HW_CAP_STOP_FW_LLDP, hw->caps); in i40e_set_hw_caps()
501 if (i40e_is_fw_ver_ge(hw, 4, 40)) { in i40e_set_hw_caps()
503 set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, hw->caps); in i40e_set_hw_caps()
505 if (i40e_is_fw_ver_ge(hw, 6, 0)) { in i40e_set_hw_caps()
507 set_bit(I40E_HW_CAP_PTP_L4, hw->caps); in i40e_set_hw_caps()
511 set_bit(I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, hw->caps); in i40e_set_hw_caps()
512 set_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw->caps); in i40e_set_hw_caps()
513 set_bit(I40E_HW_CAP_RSS_AQ, hw->caps); in i40e_set_hw_caps()
514 set_bit(I40E_HW_CAP_128_QP_RSS, hw->caps); in i40e_set_hw_caps()
515 set_bit(I40E_HW_CAP_ATR_EVICT, hw->caps); in i40e_set_hw_caps()
516 set_bit(I40E_HW_CAP_WB_ON_ITR, hw->caps); in i40e_set_hw_caps()
517 set_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, hw->caps); in i40e_set_hw_caps()
518 set_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, hw->caps); in i40e_set_hw_caps()
519 set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, hw->caps); in i40e_set_hw_caps()
520 set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, hw->caps); in i40e_set_hw_caps()
521 set_bit(I40E_HW_CAP_PTP_L4, hw->caps); in i40e_set_hw_caps()
522 set_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, hw->caps); in i40e_set_hw_caps()
523 set_bit(I40E_HW_CAP_OUTER_UDP_CSUM, hw->caps); in i40e_set_hw_caps()
525 if (rd32(hw, I40E_GLQF_FDEVICTENA(1)) != in i40e_set_hw_caps()
527 hw_warn(hw, "FD EVICT PCTYPES are not right, disable FD HW EVICT\n"); in i40e_set_hw_caps()
528 clear_bit(I40E_HW_CAP_ATR_EVICT, hw->caps); in i40e_set_hw_caps()
531 if (i40e_is_aq_api_ver_ge(hw, 1, in i40e_set_hw_caps()
533 set_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps); in i40e_set_hw_caps()
535 if (i40e_is_aq_api_ver_ge(hw, 1, in i40e_set_hw_caps()
537 set_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps); in i40e_set_hw_caps()
539 if (i40e_is_aq_api_ver_ge(hw, 1, in i40e_set_hw_caps()
541 set_bit(I40E_HW_CAP_X722_FEC_REQUEST, hw->caps); in i40e_set_hw_caps()
549 if (i40e_is_aq_api_ver_ge(hw, 1, 5)) in i40e_set_hw_caps()
550 set_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw->caps); in i40e_set_hw_caps()
553 if (i40e_is_aq_api_ver_ge(hw, 1, 7)) in i40e_set_hw_caps()
554 set_bit(I40E_HW_CAP_802_1AD, hw->caps); in i40e_set_hw_caps()
556 if (i40e_is_aq_api_ver_ge(hw, 1, 8)) in i40e_set_hw_caps()
557 set_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps); in i40e_set_hw_caps()
559 if (i40e_is_aq_api_ver_ge(hw, 1, 9)) in i40e_set_hw_caps()
560 set_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps); in i40e_set_hw_caps()
565 * @hw: pointer to the hardware structure
568 * in the hw->aq structure:
569 * - hw->aq.num_asq_entries
570 * - hw->aq.num_arq_entries
571 * - hw->aq.arq_buf_size
572 * - hw->aq.asq_buf_size
574 int i40e_init_adminq(struct i40e_hw *hw) in i40e_init_adminq() argument
582 if ((hw->aq.num_arq_entries == 0) || in i40e_init_adminq()
583 (hw->aq.num_asq_entries == 0) || in i40e_init_adminq()
584 (hw->aq.arq_buf_size == 0) || in i40e_init_adminq()
585 (hw->aq.asq_buf_size == 0)) { in i40e_init_adminq()
591 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; in i40e_init_adminq()
594 ret_code = i40e_init_asq(hw); in i40e_init_adminq()
599 ret_code = i40e_init_arq(hw); in i40e_init_adminq()
608 ret_code = i40e_aq_get_firmware_version(hw, in i40e_init_adminq()
609 &hw->aq.fw_maj_ver, in i40e_init_adminq()
610 &hw->aq.fw_min_ver, in i40e_init_adminq()
611 &hw->aq.fw_build, in i40e_init_adminq()
612 &hw->aq.api_maj_ver, in i40e_init_adminq()
613 &hw->aq.api_min_ver, in i40e_init_adminq()
619 i40e_resume_aq(hw); in i40e_init_adminq()
627 i40e_set_hw_caps(hw); in i40e_init_adminq()
630 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, in i40e_init_adminq()
631 &hw->nvm.version); in i40e_init_adminq()
632 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); in i40e_init_adminq()
633 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); in i40e_init_adminq()
634 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; in i40e_init_adminq()
635 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); in i40e_init_adminq()
636 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), in i40e_init_adminq()
638 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), in i40e_init_adminq()
640 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; in i40e_init_adminq()
642 if (i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR + 1, 0)) { in i40e_init_adminq()
648 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); in i40e_init_adminq()
649 hw->nvm_release_on_done = false; in i40e_init_adminq()
650 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_init_adminq()
658 i40e_shutdown_arq(hw); in i40e_init_adminq()
660 i40e_shutdown_asq(hw); in i40e_init_adminq()
669 * @hw: pointer to the hardware structure
671 void i40e_shutdown_adminq(struct i40e_hw *hw) in i40e_shutdown_adminq() argument
673 if (i40e_check_asq_alive(hw)) in i40e_shutdown_adminq()
674 i40e_aq_queue_shutdown(hw, true); in i40e_shutdown_adminq()
676 i40e_shutdown_asq(hw); in i40e_shutdown_adminq()
677 i40e_shutdown_arq(hw); in i40e_shutdown_adminq()
679 if (hw->nvm_buff.va) in i40e_shutdown_adminq()
680 i40e_free_virt_mem(hw, &hw->nvm_buff); in i40e_shutdown_adminq()
685 * @hw: pointer to the hardware structure
689 static u16 i40e_clean_asq(struct i40e_hw *hw) in i40e_clean_asq() argument
691 struct i40e_adminq_ring *asq = &(hw->aq.asq); in i40e_clean_asq()
699 while (rd32(hw, I40E_PF_ATQH) != ntc) { in i40e_clean_asq()
700 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_clean_asq()
701 "ntc %d head %d.\n", ntc, rd32(hw, I40E_PF_ATQH)); in i40e_clean_asq()
707 cb_func(hw, &desc_cb); in i40e_clean_asq()
725 * @hw: pointer to the hw struct
730 static bool i40e_asq_done(struct i40e_hw *hw) in i40e_asq_done() argument
735 return rd32(hw, I40E_PF_ATQH) == hw->aq.asq.next_to_use; in i40e_asq_done()
741 * @hw: pointer to the hw struct
752 i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, in i40e_asq_send_command_atomic_exec() argument
767 if (hw->aq.asq.count == 0) { in i40e_asq_send_command_atomic_exec()
768 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
774 hw->aq.asq_last_status = I40E_AQ_RC_OK; in i40e_asq_send_command_atomic_exec()
776 val = rd32(hw, I40E_PF_ATQH); in i40e_asq_send_command_atomic_exec()
777 if (val >= hw->aq.num_asq_entries) { in i40e_asq_send_command_atomic_exec()
778 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
784 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
806 if (buff_size > hw->aq.asq_buf_size) { in i40e_asq_send_command_atomic_exec()
807 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
816 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
830 if (i40e_clean_asq(hw) == 0) { in i40e_asq_send_command_atomic_exec()
831 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
839 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
846 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); in i40e_asq_send_command_atomic_exec()
861 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); in i40e_asq_send_command_atomic_exec()
862 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, in i40e_asq_send_command_atomic_exec()
864 (hw->aq.asq.next_to_use)++; in i40e_asq_send_command_atomic_exec()
865 if (hw->aq.asq.next_to_use == hw->aq.asq.count) in i40e_asq_send_command_atomic_exec()
866 hw->aq.asq.next_to_use = 0; in i40e_asq_send_command_atomic_exec()
868 wr32(hw, I40E_PF_ATQT, hw->aq.asq.next_to_use); in i40e_asq_send_command_atomic_exec()
880 if (i40e_asq_done(hw)) in i40e_asq_send_command_atomic_exec()
889 } while (total_delay < hw->aq.asq_cmd_timeout); in i40e_asq_send_command_atomic_exec()
893 if (i40e_asq_done(hw)) { in i40e_asq_send_command_atomic_exec()
899 i40e_debug(hw, in i40e_asq_send_command_atomic_exec()
914 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; in i40e_asq_send_command_atomic_exec()
917 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_asq_send_command_atomic_exec()
919 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); in i40e_asq_send_command_atomic_exec()
928 if (rd32(hw, I40E_PF_ATQLEN) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command_atomic_exec()
929 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
933 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command_atomic_exec()
945 * @hw: pointer to the hw struct
956 i40e_asq_send_command_atomic(struct i40e_hw *hw, in i40e_asq_send_command_atomic() argument
965 mutex_lock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic()
966 status = i40e_asq_send_command_atomic_exec(hw, desc, buff, buff_size, in i40e_asq_send_command_atomic()
970 mutex_unlock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic()
975 i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc, in i40e_asq_send_command() argument
979 return i40e_asq_send_command_atomic(hw, desc, buff, buff_size, in i40e_asq_send_command()
985 * @hw: pointer to the hw struct
995 * to avoid race conditions in access to hw->aq.asq_last_status.
998 i40e_asq_send_command_atomic_v2(struct i40e_hw *hw, in i40e_asq_send_command_atomic_v2() argument
1008 mutex_lock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic_v2()
1009 status = i40e_asq_send_command_atomic_exec(hw, desc, buff, in i40e_asq_send_command_atomic_v2()
1014 *aq_status = hw->aq.asq_last_status; in i40e_asq_send_command_atomic_v2()
1015 mutex_unlock(&hw->aq.asq_mutex); in i40e_asq_send_command_atomic_v2()
1020 i40e_asq_send_command_v2(struct i40e_hw *hw, struct i40e_aq_desc *desc, in i40e_asq_send_command_v2() argument
1025 return i40e_asq_send_command_atomic_v2(hw, desc, buff, buff_size, in i40e_asq_send_command_v2()
1047 * @hw: pointer to the hw struct
1055 int i40e_clean_arq_element(struct i40e_hw *hw, in i40e_clean_arq_element() argument
1059 u16 ntc = hw->aq.arq.next_to_clean; in i40e_clean_arq_element()
1072 mutex_lock(&hw->aq.arq_mutex); in i40e_clean_arq_element()
1074 if (hw->aq.arq.count == 0) { in i40e_clean_arq_element()
1075 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_clean_arq_element()
1082 ntu = rd32(hw, I40E_PF_ARQH) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
1090 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); in i40e_clean_arq_element()
1093 hw->aq.arq_last_status = in i40e_clean_arq_element()
1098 i40e_debug(hw, in i40e_clean_arq_element()
1101 hw->aq.arq_last_status); in i40e_clean_arq_element()
1108 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, in i40e_clean_arq_element()
1111 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); in i40e_clean_arq_element()
1112 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, in i40e_clean_arq_element()
1113 hw->aq.arq_buf_size); in i40e_clean_arq_element()
1119 bi = &hw->aq.arq.r.arq_bi[ntc]; in i40e_clean_arq_element()
1123 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_clean_arq_element()
1130 wr32(hw, I40E_PF_ARQT, ntc); in i40e_clean_arq_element()
1133 if (ntc == hw->aq.num_arq_entries) in i40e_clean_arq_element()
1135 hw->aq.arq.next_to_clean = ntc; in i40e_clean_arq_element()
1136 hw->aq.arq.next_to_use = ntu; in i40e_clean_arq_element()
1138 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc); in i40e_clean_arq_element()
1142 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); in i40e_clean_arq_element()
1144 mutex_unlock(&hw->aq.arq_mutex); in i40e_clean_arq_element()
1149 static void i40e_resume_aq(struct i40e_hw *hw) in i40e_resume_aq() argument
1152 hw->aq.asq.next_to_use = 0; in i40e_resume_aq()
1153 hw->aq.asq.next_to_clean = 0; in i40e_resume_aq()
1155 i40e_config_asq_regs(hw); in i40e_resume_aq()
1157 hw->aq.arq.next_to_use = 0; in i40e_resume_aq()
1158 hw->aq.arq.next_to_clean = 0; in i40e_resume_aq()
1160 i40e_config_arq_regs(hw); in i40e_resume_aq()