Lines Matching refs:fm10k_write_reg
22 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); in fm10k_reset_hw_pf()
25 fm10k_write_reg(hw, FM10K_ITR2(0), 0); in fm10k_reset_hw_pf()
26 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); in fm10k_reset_hw_pf()
32 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); in fm10k_reset_hw_pf()
33 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); in fm10k_reset_hw_pf()
53 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); in fm10k_reset_hw_pf()
91 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); in fm10k_init_hw_pf()
92 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), in fm10k_init_hw_pf()
97 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); in fm10k_init_hw_pf()
100 fm10k_write_reg(hw, FM10K_ITR2(0), 0); in fm10k_init_hw_pf()
103 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); in fm10k_init_hw_pf()
107 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); in fm10k_init_hw_pf()
110 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); in fm10k_init_hw_pf()
118 fm10k_write_reg(hw, FM10K_TQDLOC(i), in fm10k_init_hw_pf()
121 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); in fm10k_init_hw_pf()
124 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), in fm10k_init_hw_pf()
129 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), in fm10k_init_hw_pf()
160 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); in fm10k_init_hw_pf()
161 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); in fm10k_init_hw_pf()
172 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); in fm10k_init_hw_pf()
236 fm10k_write_reg(hw, reg, vlan_table ^ mask); in fm10k_update_vlan_pf()
432 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); in fm10k_update_int_moderator_pf()
441 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); in fm10k_update_int_moderator_pf()
445 fm10k_write_reg(hw, FM10K_ITR2(0), i); in fm10k_update_int_moderator_pf()
448 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); in fm10k_update_int_moderator_pf()
528 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); in fm10k_configure_dglort_map_pf()
529 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); in fm10k_configure_dglort_map_pf()
547 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); in fm10k_configure_dglort_map_pf()
570 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); in fm10k_configure_dglort_map_pf()
571 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); in fm10k_configure_dglort_map_pf()
650 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); in fm10k_iov_assign_resources_pf()
651 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); in fm10k_iov_assign_resources_pf()
652 fm10k_write_reg(hw, FM10K_TC_CREDIT(i), in fm10k_iov_assign_resources_pf()
658 fm10k_write_reg(hw, FM10K_MBMEM(i), 0); in fm10k_iov_assign_resources_pf()
661 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); in fm10k_iov_assign_resources_pf()
662 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); in fm10k_iov_assign_resources_pf()
666 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); in fm10k_iov_assign_resources_pf()
667 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | in fm10k_iov_assign_resources_pf()
669 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); in fm10k_iov_assign_resources_pf()
677 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); in fm10k_iov_assign_resources_pf()
679 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); in fm10k_iov_assign_resources_pf()
683 fm10k_write_reg(hw, FM10K_ITR2(0), in fm10k_iov_assign_resources_pf()
693 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); in fm10k_iov_assign_resources_pf()
694 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), in fm10k_iov_assign_resources_pf()
697 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), in fm10k_iov_assign_resources_pf()
700 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), in fm10k_iov_assign_resources_pf()
705 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); in fm10k_iov_assign_resources_pf()
706 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); in fm10k_iov_assign_resources_pf()
711 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); in fm10k_iov_assign_resources_pf()
712 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); in fm10k_iov_assign_resources_pf()
718 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); in fm10k_iov_assign_resources_pf()
719 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); in fm10k_iov_assign_resources_pf()
780 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); in fm10k_iov_configure_tc_pf()
781 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); in fm10k_iov_configure_tc_pf()
782 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); in fm10k_iov_configure_tc_pf()
815 fm10k_write_reg(hw, FM10K_ITR2(0), i); in fm10k_iov_assign_int_moderator_pf()
817 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); in fm10k_iov_assign_int_moderator_pf()
874 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); in fm10k_iov_assign_default_mac_vlan_pf()
891 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); in fm10k_iov_assign_default_mac_vlan_pf()
892 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); in fm10k_iov_assign_default_mac_vlan_pf()
920 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); in fm10k_iov_assign_default_mac_vlan_pf()
921 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); in fm10k_iov_assign_default_mac_vlan_pf()
927 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale << in fm10k_iov_assign_default_mac_vlan_pf()
932 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); in fm10k_iov_assign_default_mac_vlan_pf()
957 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32)); in fm10k_iov_reset_resources_pf()
975 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); in fm10k_iov_reset_resources_pf()
976 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); in fm10k_iov_reset_resources_pf()
996 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); in fm10k_iov_reset_resources_pf()
997 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); in fm10k_iov_reset_resources_pf()
998 fm10k_write_reg(hw, FM10K_RXDCTL(i), in fm10k_iov_reset_resources_pf()
1001 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); in fm10k_iov_reset_resources_pf()
1005 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); in fm10k_iov_reset_resources_pf()
1006 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); in fm10k_iov_reset_resources_pf()
1007 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), in fm10k_iov_reset_resources_pf()
1018 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); in fm10k_iov_reset_resources_pf()
1020 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); in fm10k_iov_reset_resources_pf()
1024 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); in fm10k_iov_reset_resources_pf()
1028 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); in fm10k_iov_reset_resources_pf()
1030 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); in fm10k_iov_reset_resources_pf()
1032 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); in fm10k_iov_reset_resources_pf()
1034 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); in fm10k_iov_reset_resources_pf()
1035 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); in fm10k_iov_reset_resources_pf()
1050 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); in fm10k_iov_reset_resources_pf()
1051 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); in fm10k_iov_reset_resources_pf()
1055 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i), in fm10k_iov_reset_resources_pf()
1058 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); in fm10k_iov_reset_resources_pf()
1059 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); in fm10k_iov_reset_resources_pf()
1064 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); in fm10k_iov_reset_resources_pf()
1065 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); in fm10k_iov_reset_resources_pf()
1531 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); in fm10k_set_dma_mask_pf()
1572 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); in fm10k_get_fault_pf()