437 		fm10k_write_reg(hw, FM10K_SWPRI_MAP(i),  in fm10k_configure_swpri_map()
878 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);  in fm10k_configure_tx_ring()
884 	fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));  in fm10k_configure_tx_ring()
885 	fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);  in fm10k_configure_tx_ring()
886 	fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);  in fm10k_configure_tx_ring()
889 	fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);  in fm10k_configure_tx_ring()
890 	fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);  in fm10k_configure_tx_ring()
905 	fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);  in fm10k_configure_tx_ring()
908 	fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),  in fm10k_configure_tx_ring()
919 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);  in fm10k_configure_tx_ring()
992 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);  in fm10k_configure_rx_ring()
998 	fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));  in fm10k_configure_rx_ring()
999 	fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);  in fm10k_configure_rx_ring()
1000 	fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);  in fm10k_configure_rx_ring()
1003 	fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);  in fm10k_configure_rx_ring()
1004 	fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);  in fm10k_configure_rx_ring()
1019 	fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);  in fm10k_configure_rx_ring()
1029 	fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);  in fm10k_configure_rx_ring()
1044 	fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);  in fm10k_configure_rx_ring()
1049 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);  in fm10k_configure_rx_ring()
1080 		fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);  in fm10k_update_rx_drop_en()
1099 		fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]);  in fm10k_configure_dglort()
1103 		fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]);  in fm10k_configure_dglort()
1118 	fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);  in fm10k_configure_dglort()
1200 	fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR),  in fm10k_msix_mbx_vf()
1339 		fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq);  in fm10k_reset_drop_on_empty()
1344 				fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl);  in fm10k_reset_drop_on_empty()
1362 			fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq);  in fm10k_reset_drop_on_empty()
1375 	fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX |  in fm10k_msix_mbx_pf()
1414 	fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR),  in fm10k_msix_mbx_pf()
1438 		fm10k_write_reg(hw, FM10K_EIMR,  in fm10k_mbx_free_irq()
1452 	fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET);  in fm10k_mbx_free_irq()
1532 	fm10k_write_reg(hw, FM10K_VFINT_MAP, itr);  in fm10k_mbx_request_irq_vf()
1535 	fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE);  in fm10k_mbx_request_irq_vf()
1666 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), other_itr);  in fm10k_mbx_request_irq_pf()
1667 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), other_itr);  in fm10k_mbx_request_irq_pf()
1668 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_sram), other_itr);  in fm10k_mbx_request_irq_pf()
1669 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_max_hold_time), other_itr);  in fm10k_mbx_request_irq_pf()
1670 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_vflr), other_itr);  in fm10k_mbx_request_irq_pf()
1673 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_mailbox), mbx_itr);  in fm10k_mbx_request_irq_pf()
1676 	fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |  in fm10k_mbx_request_irq_pf()
1686 	fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE);  in fm10k_mbx_request_irq_pf()