Lines Matching +full:ultra +full:- +full:low +full:- +full:power

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI	0x01000000	/* ME PCIm-to-PCI active */
43 #define E1000_FWSM_ULP_CFG_DONE		0x00000400	/* Low power cfg done */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
106 #define E1000_PCH2_RAR_ENTRIES	5	/* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES	12	/* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
169 /* I218 Ultra Low Power Configuration 1 Register */
192 /* Strapping Option Register - RO */
201 #define HV_OEM_BITS_LPLU	0x0004	/* Low Power Link Up */
203 #define HV_OEM_BITS_RESTART_AN	0x0400	/* Restart Auto-negotiation */
214 /* PHY Power Management Control */
229 /* Low Power Idle GPIO Control */
233 /* PHY Low Power Idle Control */