316 		e_dbg("Failed to initialize PHY flow\n");  in e1000_init_phy_workarounds_pchlan()
367 			e_dbg("Required LANPHYPC toggle blocked by ME\n");  in e1000_init_phy_workarounds_pchlan()
559 			e_dbg("Cannot determine PHY addr. Erroring out\n");  in e1000_init_phy_params_ich8lan()
645 			e_dbg("ERROR: Flash registers not mapped\n");  in e1000_init_nvm_params_ich8lan()
1049 			e_dbg("max_frame_size not set.\n");  in e1000_platform_pm_pch_lpt()
1055 			e_dbg("Speed not set.\n");  in e1000_platform_pm_pch_lpt()
1080 			e_dbg("Invalid LTR latency scale %d\n", scale);  in e1000_platform_pm_pch_lpt()
1199 		e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",  in e1000_enable_ulp_lpt_lp()
1210 		e_dbg("Failed to force SMBUS: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1277 		e_dbg("Error in ULP enable flow: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1344 			e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",  in e1000_disable_ulp_lpt_lp()
1441 		e_dbg("Error in ULP disable flow: %d\n", ret_val);  in e1000_disable_ulp_lpt_lp()
1711 		e_dbg("Error configuring flow control\n");  in e1000_check_for_copper_link_ich8lan()
1822 		e_dbg("contention for Phy access\n");  in e1000_acquire_swflag_ich8lan()
1836 		e_dbg("SW has already locked the resource.\n");  in e1000_acquire_swflag_ich8lan()
1856 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",  in e1000_acquire_swflag_ich8lan()
1888 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");  in e1000_release_swflag_ich8lan()
1987 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",  in e1000_rar_set_pch2lan()
1992 	e_dbg("Failed to write receive address at index %d\n", index);  in e1000_rar_set_pch2lan()
2102 	e_dbg("Failed to write receive address at index %d\n", index);  in e1000_rar_set_pch_lpt()
2158 			e_dbg("Unsupported SMB frequency in PHY\n");  in e1000_write_smbus_addr()
2927 		e_dbg("LAN_INIT_DONE not set, increase timeout\n");  in e1000_lan_init_done_ich8lan()
3284 		e_dbg("ERROR: No valid NVM bank present\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3298 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3327 		e_dbg("ERROR: No valid NVM bank present\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3355 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_read_nvm_spt()
3364 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_read_nvm_spt()
3420 		e_dbg("NVM read error: %d\n", ret_val);  in e1000_read_nvm_spt()
3446 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_read_nvm_ich8lan()
3455 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_read_nvm_ich8lan()
3480 		e_dbg("NVM read error: %d\n", ret_val);  in e1000_read_nvm_ich8lan()
3501 		e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");  in e1000_flash_cycle_init_ich8lan()
3557 			e_dbg("Flash controller busy, cannot get access\n");  in e1000_flash_cycle_init_ich8lan()
3735 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data_ich8lan()
3810 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data32_ich8lan()
3837 		e_dbg("nvm parameter(s) out of bounds\n");  in e1000_write_nvm_ich8lan()
3887 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_update_nvm_checksum_spt()
3953 		e_dbg("Flash commit failed.\n");  in e1000_update_nvm_checksum_spt()
4009 		e_dbg("NVM update error: %d\n", ret_val);  in e1000_update_nvm_checksum_spt()
4048 		e_dbg("Could not detect valid bank, assuming bank 0\n");  in e1000_update_nvm_checksum_ich8lan()
4110 		e_dbg("Flash commit failed.\n");  in e1000_update_nvm_checksum_ich8lan()
4160 		e_dbg("NVM update error: %d\n", ret_val);  in e1000_update_nvm_checksum_ich8lan()
4209 		e_dbg("NVM Checksum valid bit not set\n");  in e1000_validate_nvm_checksum_ich8lan()
4349 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data_ich8lan()
4433 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data32_ich8lan()
4479 		e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);  in e1000_retry_write_flash_dword_ich8lan()
4511 		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);  in e1000_retry_write_flash_byte_ich8lan()
4650 		e_dbg("NVM Read Error\n");  in e1000_valid_led_default_ich8lan()
4776 		e_dbg("PCI-E Master disable polling has failed.\n");  in e1000_reset_hw_ich8lan()
4778 	e_dbg("Masking off all interrupts\n");  in e1000_reset_hw_ich8lan()
4828 	e_dbg("Issuing a global reset to ich8lan\n");  in e1000_reset_hw_ich8lan()
4896 		e_dbg("Error initializing identification LED\n");  in e1000_init_hw_ich8lan()
4902 	e_dbg("Zeroing the MTA\n");  in e1000_init_hw_ich8lan()
5079 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);  in e1000_setup_link_ich8lan()
5319 		e_dbg("Workaround applies to ICH8 only.\n");  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5555 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);  in e1000_resume_workarounds_pchlan()
5569 			e_dbg("Failed to setup iRST\n");  in e1000_resume_workarounds_pchlan()
5599 			e_dbg("Error %d in resume workarounds\n", ret_val);  in e1000_resume_workarounds_pchlan()
5764 			e_dbg("Auto Read Done did not complete\n");  in e1000_get_cfg_done_ich8lan()
5774 		e_dbg("PHY Reset Asserted not set - needs delay\n");  in e1000_get_cfg_done_ich8lan()
5785 			e_dbg("EEPROM not present\n");  in e1000_get_cfg_done_ich8lan()