Lines Matching +full:0 +full:x4140
27 #define E1000E_PRIV_FLAGS_S0IX_ENABLED BIT(0)
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
181 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in e1000_get_link_ksettings()
208 return 0; in e1000_get_link_ksettings()
215 mac->autoneg = 0; in e1000_set_spd_dplx()
259 return 0; in e1000_set_spd_dplx()
271 int ret_val = 0; in e1000_set_link_ksettings()
326 /* fix up the value for auto (3 => 0) as zero is mapped in e1000_set_link_ksettings()
372 int retval = 0; in e1000_set_pauseparam()
441 memset(p, 0, E1000_REGS_LEN * sizeof(u32)); in e1000_get_regs()
447 regs_buff[0] = er32(CTRL); in e1000_get_regs()
451 regs_buff[3] = er32(RDLEN(0)); in e1000_get_regs()
452 regs_buff[4] = er32(RDH(0)); in e1000_get_regs()
453 regs_buff[5] = er32(RDT(0)); in e1000_get_regs()
457 regs_buff[8] = er32(TDLEN(0)); in e1000_get_regs()
458 regs_buff[9] = er32(TDH(0)); in e1000_get_regs()
459 regs_buff[10] = er32(TDT(0)); in e1000_get_regs()
462 regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ in e1000_get_regs()
470 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
471 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
472 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
476 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ in e1000_get_regs()
482 regs_buff[21] = 0; /* was idle_errors */ in e1000_get_regs()
502 int ret_val = 0; in e1000_get_eeprom()
505 if (eeprom->len == 0) in e1000_get_eeprom()
523 for (i = 0; i < last_word - first_word + 1; i++) { in e1000_get_eeprom()
533 memset(eeprom_buff, 0xff, sizeof(u16) * in e1000_get_eeprom()
537 for (i = 0; i < last_word - first_word + 1; i++) in e1000_get_eeprom()
557 int ret_val = 0; in e1000_set_eeprom()
560 if (eeprom->len == 0) in e1000_set_eeprom()
583 ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]); in e1000_set_eeprom()
596 for (i = 0; i < last_word - first_word + 1; i++) in e1000_set_eeprom()
601 for (i = 0; i < last_word - first_word + 1; i++) in e1000_set_eeprom()
636 FIELD_GET(0xF000, adapter->eeprom_vers), in e1000_get_drvinfo()
637 FIELD_GET(0x0FF0, adapter->eeprom_vers), in e1000_get_drvinfo()
638 (adapter->eeprom_vers & 0x000F)); in e1000_get_drvinfo()
664 int err = 0, size = sizeof(struct e1000_ring); in e1000_set_ringparam()
682 return 0; in e1000_set_ringparam()
766 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF in reg_pattern_test()
768 for (pat = 0; pat < ARRAY_SIZE(test); pat++) { in reg_pattern_test()
773 e_err("pattern test failed (reg 0x%05X): got 0x%08X expected 0x%08X\n", in reg_pattern_test()
791 e_err("set/check test failed (reg 0x%05X): got 0x%08X expected 0x%08X\n", in reg_set_and_check()
803 } while (0)
805 REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
811 } while (0)
823 u32 wlock_mac = 0; in e1000_reg_test()
833 toggle = 0x7FFFF3FF; in e1000_reg_test()
836 toggle = 0x7FFFF033; in e1000_reg_test()
845 e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n", in e1000_reg_test()
854 REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
855 REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
856 REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
857 REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
860 REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF); in e1000_reg_test()
861 REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
862 REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF); in e1000_reg_test()
863 REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
864 REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
865 REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8); in e1000_reg_test()
866 REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
867 REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF); in e1000_reg_test()
868 REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
869 REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF); in e1000_reg_test()
871 REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000); in e1000_reg_test()
873 before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE); in e1000_reg_test()
874 REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB); in e1000_reg_test()
875 REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000); in e1000_reg_test()
877 REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF); in e1000_reg_test()
878 REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); in e1000_reg_test()
880 REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF); in e1000_reg_test()
881 REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF); in e1000_reg_test()
882 REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF); in e1000_reg_test()
883 mask = 0x8003FFFF; in e1000_reg_test()
906 for (i = 0; i < mac->rar_entry_count; i++) { in e1000_reg_test()
919 /* SHRAH[0,1,2] different than previous */ in e1000_reg_test()
921 mask &= 0xFFF4FFFF; in e1000_reg_test()
922 /* SHRAH[3] different than SHRAH[0,1,2] */ in e1000_reg_test()
926 if (i > 0) in e1000_reg_test()
931 0xFFFFFFFF); in e1000_reg_test()
937 for (i = 0; i < mac->mta_reg_count; i++) in e1000_reg_test()
938 REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF); in e1000_reg_test()
940 *data = 0; in e1000_reg_test()
942 return 0; in e1000_reg_test()
948 u16 checksum = 0; in e1000_eeprom_test()
951 *data = 0; in e1000_eeprom_test()
953 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { in e1000_eeprom_test()
954 if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) { in e1000_eeprom_test()
987 int ret_val = 0; in e1000_intr_test()
990 *data = 0; in e1000_intr_test()
1002 shared_int = 0; in e1000_intr_test()
1012 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
1017 for (i = 0; i < 10; i++) { in e1000_intr_test()
1025 case 0x00000100: in e1000_intr_test()
1042 adapter->test_icr = 0; in e1000_intr_test()
1060 adapter->test_icr = 0; in e1000_intr_test()
1078 adapter->test_icr = 0; in e1000_intr_test()
1079 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test()
1080 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test()
1092 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
1118 for (i = 0; i < tx_ring->count; i++) { in e1000_free_desc_rings()
1131 for (i = 0; i < rx_ring->count; i++) { in e1000_free_desc_rings()
1189 tx_ring->next_to_use = 0; in e1000_setup_desc_rings()
1190 tx_ring->next_to_clean = 0; in e1000_setup_desc_rings()
1192 ew32(TDBAL(0), ((u64)tx_ring->dma & 0x00000000FFFFFFFF)); in e1000_setup_desc_rings()
1193 ew32(TDBAH(0), ((u64)tx_ring->dma >> 32)); in e1000_setup_desc_rings()
1194 ew32(TDLEN(0), tx_ring->count * sizeof(struct e1000_tx_desc)); in e1000_setup_desc_rings()
1195 ew32(TDH(0), 0); in e1000_setup_desc_rings()
1196 ew32(TDT(0), 0); in e1000_setup_desc_rings()
1201 for (i = 0; i < tx_ring->count; i++) { in e1000_setup_desc_rings()
1227 tx_desc->upper.data = 0; in e1000_setup_desc_rings()
1249 rx_ring->next_to_use = 0; in e1000_setup_desc_rings()
1250 rx_ring->next_to_clean = 0; in e1000_setup_desc_rings()
1255 ew32(RDBAL(0), ((u64)rx_ring->dma & 0xFFFFFFFF)); in e1000_setup_desc_rings()
1256 ew32(RDBAH(0), ((u64)rx_ring->dma >> 32)); in e1000_setup_desc_rings()
1257 ew32(RDLEN(0), rx_ring->size); in e1000_setup_desc_rings()
1258 ew32(RDH(0), 0); in e1000_setup_desc_rings()
1259 ew32(RDT(0), 0); in e1000_setup_desc_rings()
1267 for (i = 0; i < rx_ring->count; i++) { in e1000_setup_desc_rings()
1289 memset(skb->data, 0x00, skb->len); in e1000_setup_desc_rings()
1292 return 0; in e1000_setup_desc_rings()
1302 e1e_wphy(&adapter->hw, 29, 0x001F); in e1000_phy_disable_receiver()
1303 e1e_wphy(&adapter->hw, 30, 0x8FFC); in e1000_phy_disable_receiver()
1304 e1e_wphy(&adapter->hw, 29, 0x001A); in e1000_phy_disable_receiver()
1305 e1e_wphy(&adapter->hw, 30, 0x8FF0); in e1000_phy_disable_receiver()
1311 u32 ctrl_reg = 0; in e1000_integrated_phy_loopback()
1312 u16 phy_reg = 0; in e1000_integrated_phy_loopback()
1313 s32 ret_val = 0; in e1000_integrated_phy_loopback()
1315 hw->mac.autoneg = 0; in e1000_integrated_phy_loopback()
1319 e1e_wphy(hw, MII_BMCR, 0x6100); in e1000_integrated_phy_loopback()
1333 return 0; in e1000_integrated_phy_loopback()
1340 e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); in e1000_integrated_phy_loopback()
1342 e1e_wphy(hw, MII_BMCR, 0x9140); in e1000_integrated_phy_loopback()
1344 e1e_wphy(hw, MII_BMCR, 0x8140); in e1000_integrated_phy_loopback()
1347 e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC); in e1000_integrated_phy_loopback()
1352 phy_reg &= ~0x0007; in e1000_integrated_phy_loopback()
1353 phy_reg |= 0x006; in e1000_integrated_phy_loopback()
1360 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1363 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1366 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1369 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
1384 e1e_rphy(hw, PHY_REG(0, 21), &phy_reg); in e1000_integrated_phy_loopback()
1385 e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3)); in e1000_integrated_phy_loopback()
1390 e1e_wphy(hw, I82577_PHY_LBK_CTRL, 0x8001); in e1000_integrated_phy_loopback()
1397 e1e_wphy(hw, MII_BMCR, 0x4140); in e1000_integrated_phy_loopback()
1418 if ((er32(STATUS) & E1000_STATUS_FD) == 0) in e1000_integrated_phy_loopback()
1432 return 0; in e1000_integrated_phy_loopback()
1470 return 0; in e1000_set_82571_fiber_loopback()
1501 #define KMRNCTRLSTA_OPMODE (0x1F << 16) in e1000_set_es2lan_mac_loopback()
1502 #define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582 in e1000_set_es2lan_mac_loopback()
1506 return 0; in e1000_set_es2lan_mac_loopback()
1518 tarc0 = er32(TARC(0)); in e1000_setup_loopback_test()
1520 tarc0 &= 0xcfffffff; in e1000_setup_loopback_test()
1522 tarc0 |= 0x20000000; in e1000_setup_loopback_test()
1523 ew32(TARC(0), tarc0); in e1000_setup_loopback_test()
1537 return 0; in e1000_setup_loopback_test()
1568 tarc0 = er32(TARC(0)); in e1000_loopback_cleanup()
1570 /* set bit 29 (value of MULR requests is now 0) */ in e1000_loopback_cleanup()
1571 tarc0 &= 0xcfffffff; in e1000_loopback_cleanup()
1572 ew32(TARC(0), tarc0); in e1000_loopback_cleanup()
1579 adapter->tx_fifo_head = 0; in e1000_loopback_cleanup()
1595 e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180); in e1000_loopback_cleanup()
1610 memset(skb->data, 0xFF, frame_size); in e1000_create_lbtest_frame()
1612 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); in e1000_create_lbtest_frame()
1613 skb->data[frame_size / 2 + 10] = 0xBE; in e1000_create_lbtest_frame()
1614 skb->data[frame_size / 2 + 12] = 0xAF; in e1000_create_lbtest_frame()
1621 if (*(skb->data + 3) == 0xFF) in e1000_check_lbtest_frame()
1622 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && in e1000_check_lbtest_frame()
1623 (*(skb->data + frame_size / 2 + 12) == 0xAF)) in e1000_check_lbtest_frame()
1624 return 0; in e1000_check_lbtest_frame()
1638 int ret_val = 0; in e1000_run_loopback_test()
1641 ew32(RDT(0), rx_ring->count - 1); in e1000_run_loopback_test()
1653 k = 0; in e1000_run_loopback_test()
1654 l = 0; in e1000_run_loopback_test()
1656 for (j = 0; j <= lc; j++) { in e1000_run_loopback_test()
1658 for (i = 0; i < 64; i++) { in e1000_run_loopback_test()
1668 k = 0; in e1000_run_loopback_test()
1670 ew32(TDT(0), k); in e1000_run_loopback_test()
1674 good_cnt = 0; in e1000_run_loopback_test()
1689 l = 0; in e1000_run_loopback_test()
1715 *data = 0; in e1000_loopback_test()
1740 *data = 0; in e1000_link_test()
1742 int i = 0; in e1000_link_test()
1806 adapter->hw.phy.autoneg_wait_to_complete = 0; in e1000_diag_test()
1823 if (e1000_reg_test(adapter, &data[0])) in e1000_diag_test()
1841 adapter->hw.phy.autoneg_wait_to_complete = 0; in e1000_diag_test()
1861 data[0] = 0; in e1000_diag_test()
1862 data[1] = 0; in e1000_diag_test()
1863 data[2] = 0; in e1000_diag_test()
1864 data[3] = 0; in e1000_diag_test()
1887 wol->supported = 0; in e1000_get_wol()
1888 wol->wolopts = 0; in e1000_get_wol()
1928 adapter->wol = 0; in e1000_set_wol()
1943 return 0; in e1000_set_wol()
1964 e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); in e1000_set_phys_id()
1979 return 0; in e1000_set_phys_id()
1994 return 0; in e1000_get_coalesce()
2021 if (adapter->itr_setting != 0) in e1000_set_coalesce()
2024 e1000e_write_itr(adapter, 0); in e1000_set_coalesce()
2026 return 0; in e1000_set_coalesce()
2041 return 0; in e1000_nway_reset()
2055 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { in e1000_get_ethtool_stats()
2066 data[i] = 0; in e1000_get_ethtool_stats()
2086 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { in e1000_get_strings()
2103 info->data = 0; in e1000_get_rxnfc()
2114 return 0; in e1000_get_rxnfc()
2142 return 0; in e1000_get_rxnfc()
2262 return 0; in e1000e_set_eee()
2273 return 0; in e1000e_get_ts_info()
2296 return 0; in e1000e_get_ts_info()
2302 u32 priv_flags = 0; in e1000e_get_priv_flags()
2327 return 0; in e1000e_set_priv_flags()