intel/e1000e/defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
11 /* Definitions for power management and wakeup registers */
16 #define E1000_WUC_APMPME	0x00000008	/* Assert PME on APM Wakeup */
17 #define E1000_WUC_PHY_WAKE	0x00000100	/* if PHY supports wakeup */
20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
21 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
22 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
23 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
24 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
25 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
46 #define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
74 /* mask to determine if packets should be dropped due to frame errors */
82 /* Same mask, but for extended and packet split descriptors */
100 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
130 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
135 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
183 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
186 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
213 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
402 #define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
408 /* This defines the bits that are set in the Interrupt Mask
433 /* Interrupt Mask Set */
483 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
519 #define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
520 #define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
527 #define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
528 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
531 #define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
541 #define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
544 #define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
545 #define E1000_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
595 #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
624 /* Mask bits for fields in Word 0x0f of the NVM */
629 /* Mask bits for fields in Word 0x1a of the NVM */
632 /* Mask bits for fields in Word 0x03 of the EEPROM */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
686 /* Bit definitions for valid PHY IDs.
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
760  * 15-5: page
761  * 4-0: register offset
784 /* Page 193 - Port Control Registers */
790 /* Page 194 - KMRN Registers */