intel/e1000e/defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 #define E1000_WUC_PHY_WAKE	0x00000100	/* if PHY supports wakeup */
37 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
46 #define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
104 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
183 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
184 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
185 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
187 #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
188 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
189 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
190 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
191 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
198 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
204 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
222 #define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
511 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
528 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
686 /* Bit definitions for valid PHY IDs.
688  * E = External
708 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
709 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
710 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
715 /* M88E1000 PHY Specific Control Register */
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
726 /* M88E1000 PHY Specific Status Register */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
756 /* BME1000 PHY Specific Control Register */
760  * 15-5: page
761  * 4-0: register offset
770 	GG82563_REG(0, 16) /* PHY Specific Control */
774 	GG82563_REG(0, 26) /* PHY Specific Control 2 */
784 /* Page 193 - Port Control Registers */
790 /* Page 194 - KMRN Registers */