732 	ew32(STATUS, toggle);  in e1000_reg_test()
741 	ew32(STATUS, before);  in e1000_reg_test()
851 	ew32(IMC, 0xFFFFFFFF);  in e1000_intr_test()
868 			ew32(IMC, mask);  in e1000_intr_test()
869 			ew32(ICS, mask);  in e1000_intr_test()
886 		ew32(IMS, mask);  in e1000_intr_test()
887 		ew32(ICS, mask);  in e1000_intr_test()
904 			ew32(IMC, ~mask & 0x00007FFF);  in e1000_intr_test()
905 			ew32(ICS, ~mask & 0x00007FFF);  in e1000_intr_test()
917 	ew32(IMC, 0xFFFFFFFF);  in e1000_intr_test()
1004 	ew32(TDBAL, ((u64)txdr->dma & 0x00000000FFFFFFFF));  in e1000_setup_desc_rings()
1005 	ew32(TDBAH, ((u64)txdr->dma >> 32));  in e1000_setup_desc_rings()
1006 	ew32(TDLEN, txdr->count * sizeof(struct e1000_tx_desc));  in e1000_setup_desc_rings()
1007 	ew32(TDH, 0);  in e1000_setup_desc_rings()
1008 	ew32(TDT, 0);  in e1000_setup_desc_rings()
1009 	ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN |  in e1000_setup_desc_rings()
1063 	ew32(RCTL, rctl & ~E1000_RCTL_EN);  in e1000_setup_desc_rings()
1064 	ew32(RDBAL, ((u64)rxdr->dma & 0xFFFFFFFF));  in e1000_setup_desc_rings()
1065 	ew32(RDBAH, ((u64)rxdr->dma >> 32));  in e1000_setup_desc_rings()
1066 	ew32(RDLEN, rxdr->size);  in e1000_setup_desc_rings()
1067 	ew32(RDH, 0);  in e1000_setup_desc_rings()
1068 	ew32(RDT, 0);  in e1000_setup_desc_rings()
1072 	ew32(RCTL, rctl);  in e1000_setup_desc_rings()
1152 	ew32(CTRL, ctrl_reg);  in e1000_nonintegrated_phy_loopback()
1247 	ew32(CTRL, ctrl_reg);  in e1000_integrated_phy_loopback()
1320 			ew32(RCTL, rctl);  in e1000_setup_loopback_test()
1338 	ew32(RCTL, rctl);  in e1000_loopback_cleanup()
1389 	ew32(RDT, rxdr->count - 1);  in e1000_run_loopback_test()
1413 		ew32(TDT, k);  in e1000_run_loopback_test()
1791 		ew32(ITR, 1000000000 / (adapter->itr * 256));  in e1000_set_coalesce()
1793 		ew32(ITR, 0);  in e1000_set_coalesce()