Lines Matching refs:mal
34 int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac) in mal_register_commac() argument
38 spin_lock_irqsave(&mal->lock, flags); in mal_register_commac()
40 MAL_DBG(mal, "reg(%08x, %08x)" NL, in mal_register_commac()
44 if ((mal->tx_chan_mask & commac->tx_chan_mask) || in mal_register_commac()
45 (mal->rx_chan_mask & commac->rx_chan_mask)) { in mal_register_commac()
46 spin_unlock_irqrestore(&mal->lock, flags); in mal_register_commac()
48 mal->index); in mal_register_commac()
52 if (list_empty(&mal->list)) in mal_register_commac()
53 napi_enable(&mal->napi); in mal_register_commac()
54 mal->tx_chan_mask |= commac->tx_chan_mask; in mal_register_commac()
55 mal->rx_chan_mask |= commac->rx_chan_mask; in mal_register_commac()
56 list_add(&commac->list, &mal->list); in mal_register_commac()
58 spin_unlock_irqrestore(&mal->lock, flags); in mal_register_commac()
63 void mal_unregister_commac(struct mal_instance *mal, in mal_unregister_commac() argument
68 spin_lock_irqsave(&mal->lock, flags); in mal_unregister_commac()
70 MAL_DBG(mal, "unreg(%08x, %08x)" NL, in mal_unregister_commac()
73 mal->tx_chan_mask &= ~commac->tx_chan_mask; in mal_unregister_commac()
74 mal->rx_chan_mask &= ~commac->rx_chan_mask; in mal_unregister_commac()
76 if (list_empty(&mal->list)) in mal_unregister_commac()
77 napi_disable(&mal->napi); in mal_unregister_commac()
79 spin_unlock_irqrestore(&mal->lock, flags); in mal_unregister_commac()
82 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size) in mal_set_rcbs() argument
84 BUG_ON(channel < 0 || channel >= mal->num_rx_chans || in mal_set_rcbs()
87 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size); in mal_set_rcbs()
92 mal->index, size, channel); in mal_set_rcbs()
96 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4); in mal_set_rcbs()
100 int mal_tx_bd_offset(struct mal_instance *mal, int channel) in mal_tx_bd_offset() argument
102 BUG_ON(channel < 0 || channel >= mal->num_tx_chans); in mal_tx_bd_offset()
107 int mal_rx_bd_offset(struct mal_instance *mal, int channel) in mal_rx_bd_offset() argument
109 BUG_ON(channel < 0 || channel >= mal->num_rx_chans); in mal_rx_bd_offset()
110 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF; in mal_rx_bd_offset()
113 void mal_enable_tx_channel(struct mal_instance *mal, int channel) in mal_enable_tx_channel() argument
117 spin_lock_irqsave(&mal->lock, flags); in mal_enable_tx_channel()
119 MAL_DBG(mal, "enable_tx(%d)" NL, channel); in mal_enable_tx_channel()
121 set_mal_dcrn(mal, MAL_TXCASR, in mal_enable_tx_channel()
122 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel)); in mal_enable_tx_channel()
124 spin_unlock_irqrestore(&mal->lock, flags); in mal_enable_tx_channel()
127 void mal_disable_tx_channel(struct mal_instance *mal, int channel) in mal_disable_tx_channel() argument
129 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel)); in mal_disable_tx_channel()
131 MAL_DBG(mal, "disable_tx(%d)" NL, channel); in mal_disable_tx_channel()
134 void mal_enable_rx_channel(struct mal_instance *mal, int channel) in mal_enable_rx_channel() argument
146 spin_lock_irqsave(&mal->lock, flags); in mal_enable_rx_channel()
148 MAL_DBG(mal, "enable_rx(%d)" NL, channel); in mal_enable_rx_channel()
150 set_mal_dcrn(mal, MAL_RXCASR, in mal_enable_rx_channel()
151 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel)); in mal_enable_rx_channel()
153 spin_unlock_irqrestore(&mal->lock, flags); in mal_enable_rx_channel()
156 void mal_disable_rx_channel(struct mal_instance *mal, int channel) in mal_disable_rx_channel() argument
166 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); in mal_disable_rx_channel()
168 MAL_DBG(mal, "disable_rx(%d)" NL, channel); in mal_disable_rx_channel()
171 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac) in mal_poll_add() argument
175 spin_lock_irqsave(&mal->lock, flags); in mal_poll_add()
177 MAL_DBG(mal, "poll_add(%p)" NL, commac); in mal_poll_add()
182 list_add_tail(&commac->poll_list, &mal->poll_list); in mal_poll_add()
184 spin_unlock_irqrestore(&mal->lock, flags); in mal_poll_add()
187 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac) in mal_poll_del() argument
191 spin_lock_irqsave(&mal->lock, flags); in mal_poll_del()
193 MAL_DBG(mal, "poll_del(%p)" NL, commac); in mal_poll_del()
197 spin_unlock_irqrestore(&mal->lock, flags); in mal_poll_del()
201 static inline void mal_enable_eob_irq(struct mal_instance *mal) in mal_enable_eob_irq() argument
203 MAL_DBG2(mal, "enable_irq" NL); in mal_enable_eob_irq()
206 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE); in mal_enable_eob_irq()
210 static inline void mal_disable_eob_irq(struct mal_instance *mal) in mal_disable_eob_irq() argument
213 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE); in mal_disable_eob_irq()
215 MAL_DBG2(mal, "disable_irq" NL); in mal_disable_eob_irq()
220 struct mal_instance *mal = dev_instance; in mal_serr() local
222 u32 esr = get_mal_dcrn(mal, MAL_ESR); in mal_serr()
225 set_mal_dcrn(mal, MAL_ESR, esr); in mal_serr()
227 MAL_DBG(mal, "SERR %08x" NL, esr); in mal_serr()
245 mal->index, esr); in mal_serr()
255 mal->index, esr); in mal_serr()
260 static inline void mal_schedule_poll(struct mal_instance *mal) in mal_schedule_poll() argument
262 if (likely(napi_schedule_prep(&mal->napi))) { in mal_schedule_poll()
263 MAL_DBG2(mal, "schedule_poll" NL); in mal_schedule_poll()
264 spin_lock(&mal->lock); in mal_schedule_poll()
265 mal_disable_eob_irq(mal); in mal_schedule_poll()
266 spin_unlock(&mal->lock); in mal_schedule_poll()
267 __napi_schedule(&mal->napi); in mal_schedule_poll()
269 MAL_DBG2(mal, "already in poll" NL); in mal_schedule_poll()
274 struct mal_instance *mal = dev_instance; in mal_txeob() local
276 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR); in mal_txeob()
278 MAL_DBG2(mal, "txeob %08x" NL, r); in mal_txeob()
280 mal_schedule_poll(mal); in mal_txeob()
281 set_mal_dcrn(mal, MAL_TXEOBISR, r); in mal_txeob()
284 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) in mal_txeob()
294 struct mal_instance *mal = dev_instance; in mal_rxeob() local
296 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR); in mal_rxeob()
298 MAL_DBG2(mal, "rxeob %08x" NL, r); in mal_rxeob()
300 mal_schedule_poll(mal); in mal_rxeob()
301 set_mal_dcrn(mal, MAL_RXEOBISR, r); in mal_rxeob()
304 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) in mal_rxeob()
314 struct mal_instance *mal = dev_instance; in mal_txde() local
316 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR); in mal_txde()
317 set_mal_dcrn(mal, MAL_TXDEIR, deir); in mal_txde()
319 MAL_DBG(mal, "txde %08x" NL, deir); in mal_txde()
324 mal->index, deir); in mal_txde()
331 struct mal_instance *mal = dev_instance; in mal_rxde() local
334 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR); in mal_rxde()
336 MAL_DBG(mal, "rxde %08x" NL, deir); in mal_rxde()
338 list_for_each(l, &mal->list) { in mal_rxde()
346 mal_schedule_poll(mal); in mal_rxde()
347 set_mal_dcrn(mal, MAL_RXDEIR, deir); in mal_rxde()
354 struct mal_instance *mal = dev_instance; in mal_int() local
355 u32 esr = get_mal_dcrn(mal, MAL_ESR); in mal_int()
371 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac) in mal_poll_disable() argument
378 napi_synchronize(&mal->napi); in mal_poll_disable()
381 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac) in mal_poll_enable() argument
391 napi_schedule(&mal->napi); in mal_poll_enable()
396 struct mal_instance *mal = container_of(napi, struct mal_instance, napi); in mal_poll() local
401 MAL_DBG2(mal, "poll(%d)" NL, budget); in mal_poll()
404 list_for_each(l, &mal->poll_list) { in mal_poll()
415 list_for_each(l, &mal->poll_list) { in mal_poll()
431 spin_lock_irqsave(&mal->lock, flags); in mal_poll()
432 mal_enable_eob_irq(mal); in mal_poll()
433 spin_unlock_irqrestore(&mal->lock, flags); in mal_poll()
437 list_for_each(l, &mal->poll_list) { in mal_poll()
444 MAL_DBG2(mal, "rotting packet" NL); in mal_poll()
448 spin_lock_irqsave(&mal->lock, flags); in mal_poll()
449 mal_disable_eob_irq(mal); in mal_poll()
450 spin_unlock_irqrestore(&mal->lock, flags); in mal_poll()
456 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received); in mal_poll()
460 static void mal_reset(struct mal_instance *mal) in mal_reset() argument
464 MAL_DBG(mal, "reset" NL); in mal_reset()
466 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR); in mal_reset()
469 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n) in mal_reset()
473 printk(KERN_ERR "mal%d: reset timeout\n", mal->index); in mal_reset()
476 int mal_get_regs_len(struct mal_instance *mal) in mal_get_regs_len() argument
482 void *mal_dump_regs(struct mal_instance *mal, void *buf) in mal_dump_regs() argument
488 hdr->version = mal->version; in mal_dump_regs()
489 hdr->index = mal->index; in mal_dump_regs()
491 regs->tx_count = mal->num_tx_chans; in mal_dump_regs()
492 regs->rx_count = mal->num_rx_chans; in mal_dump_regs()
494 regs->cfg = get_mal_dcrn(mal, MAL_CFG); in mal_dump_regs()
495 regs->esr = get_mal_dcrn(mal, MAL_ESR); in mal_dump_regs()
496 regs->ier = get_mal_dcrn(mal, MAL_IER); in mal_dump_regs()
497 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR); in mal_dump_regs()
498 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR); in mal_dump_regs()
499 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR); in mal_dump_regs()
500 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR); in mal_dump_regs()
501 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR); in mal_dump_regs()
502 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR); in mal_dump_regs()
503 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR); in mal_dump_regs()
504 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR); in mal_dump_regs()
507 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i)); in mal_dump_regs()
510 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i)); in mal_dump_regs()
511 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i)); in mal_dump_regs()
518 struct mal_instance *mal; in mal_probe() local
527 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL); in mal_probe()
528 if (!mal) in mal_probe()
531 mal->index = index; in mal_probe()
532 mal->ofdev = ofdev; in mal_probe()
533 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1; in mal_probe()
535 MAL_DBG(mal, "probe" NL); in mal_probe()
545 mal->num_tx_chans = prop[0]; in mal_probe()
555 mal->num_rx_chans = prop[0]; in mal_probe()
564 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100); in mal_probe()
565 if (!DCR_MAP_OK(mal->dcr_host)) { in mal_probe()
575 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT | in mal_probe()
585 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); in mal_probe()
586 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1); in mal_probe()
587 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2); in mal_probe()
589 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { in mal_probe()
590 mal->txde_irq = mal->rxde_irq = mal->serr_irq; in mal_probe()
592 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3); in mal_probe()
593 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4); in mal_probe()
596 if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq || in mal_probe()
597 !mal->txde_irq || !mal->rxde_irq) { in mal_probe()
604 INIT_LIST_HEAD(&mal->poll_list); in mal_probe()
605 INIT_LIST_HEAD(&mal->list); in mal_probe()
606 spin_lock_init(&mal->lock); in mal_probe()
608 mal->dummy_dev = alloc_netdev_dummy(0); in mal_probe()
609 if (!mal->dummy_dev) { in mal_probe()
614 netif_napi_add_weight(mal->dummy_dev, &mal->napi, mal_poll, in mal_probe()
618 mal_reset(mal); in mal_probe()
621 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT; in mal_probe()
631 set_mal_dcrn(mal, MAL_CFG, cfg); in mal_probe()
634 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32); in mal_probe()
635 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32); in mal_probe()
638 (NUM_TX_BUFF * mal->num_tx_chans + in mal_probe()
639 NUM_RX_BUFF * mal->num_rx_chans); in mal_probe()
640 mal->bd_virt = dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma, in mal_probe()
642 if (mal->bd_virt == NULL) { in mal_probe()
647 for (i = 0; i < mal->num_tx_chans; ++i) in mal_probe()
648 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma + in mal_probe()
650 mal_tx_bd_offset(mal, i)); in mal_probe()
652 for (i = 0; i < mal->num_rx_chans; ++i) in mal_probe()
653 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma + in mal_probe()
655 mal_rx_bd_offset(mal, i)); in mal_probe()
657 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { in mal_probe()
667 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal); in mal_probe()
670 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal); in mal_probe()
673 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal); in mal_probe()
676 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal); in mal_probe()
679 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal); in mal_probe()
684 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS); in mal_probe()
687 mal_enable_eob_irq(mal); in mal_probe()
691 mal->version, ofdev->dev.of_node, in mal_probe()
692 mal->num_tx_chans, mal->num_rx_chans); in mal_probe()
696 platform_set_drvdata(ofdev, mal); in mal_probe()
701 free_irq(mal->rxde_irq, mal); in mal_probe()
703 free_irq(mal->txeob_irq, mal); in mal_probe()
705 free_irq(mal->txde_irq, mal); in mal_probe()
707 free_irq(mal->serr_irq, mal); in mal_probe()
709 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma); in mal_probe()
711 free_netdev(mal->dummy_dev); in mal_probe()
713 dcr_unmap(mal->dcr_host, 0x100); in mal_probe()
715 kfree(mal); in mal_probe()
722 struct mal_instance *mal = platform_get_drvdata(ofdev); in mal_remove() local
724 MAL_DBG(mal, "remove" NL); in mal_remove()
727 napi_disable(&mal->napi); in mal_remove()
729 if (!list_empty(&mal->list)) in mal_remove()
733 mal->index); in mal_remove()
735 free_irq(mal->serr_irq, mal); in mal_remove()
736 free_irq(mal->txde_irq, mal); in mal_remove()
737 free_irq(mal->txeob_irq, mal); in mal_remove()
738 free_irq(mal->rxde_irq, mal); in mal_remove()
739 free_irq(mal->rxeob_irq, mal); in mal_remove()
741 mal_reset(mal); in mal_remove()
743 free_netdev(mal->dummy_dev); in mal_remove()
745 dcr_unmap(mal->dcr_host, 0x100); in mal_remove()
749 (NUM_TX_BUFF * mal->num_tx_chans + in mal_remove()
750 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt, in mal_remove()
751 mal->bd_dma); in mal_remove()
752 kfree(mal); in mal_remove()