Lines Matching refs:cb0
977 struct hcp_ehea_port_cb0 *cb0; in ehea_sense_port_attr() local
980 cb0 = (void *)get_zeroed_page(GFP_ATOMIC); in ehea_sense_port_attr()
981 if (!cb0) { in ehea_sense_port_attr()
990 cb0); in ehea_sense_port_attr()
997 port->mac_addr = cb0->port_mac_addr << 16; in ehea_sense_port_attr()
1005 switch (cb0->port_speed) { in ehea_sense_port_attr()
1037 port->num_mcs = cb0->num_default_qps; in ehea_sense_port_attr()
1041 port->num_def_qps = cb0->num_default_qps; in ehea_sense_port_attr()
1053 ehea_dump(cb0, sizeof(*cb0), "ehea_sense_port_attr"); in ehea_sense_port_attr()
1054 free_page((unsigned long)cb0); in ehea_sense_port_attr()
1350 struct hcp_ehea_port_cb0 *cb0; in ehea_configure_port() local
1353 cb0 = (void *)get_zeroed_page(GFP_KERNEL); in ehea_configure_port()
1354 if (!cb0) in ehea_configure_port()
1357 cb0->port_rc = EHEA_BMASK_SET(PXLY_RC_VALID, 1) in ehea_configure_port()
1367 cb0->default_qpn_arr[i] = in ehea_configure_port()
1370 cb0->default_qpn_arr[i] = in ehea_configure_port()
1374 ehea_dump(cb0, sizeof(*cb0), "ehea_configure_port"); in ehea_configure_port()
1381 H_PORT_CB0, mask, cb0); in ehea_configure_port()
1389 free_page((unsigned long)cb0); in ehea_configure_port()
1719 struct hcp_ehea_port_cb0 *cb0; in ehea_set_mac_addr() local
1728 cb0 = (void *)get_zeroed_page(GFP_KERNEL); in ehea_set_mac_addr()
1729 if (!cb0) { in ehea_set_mac_addr()
1735 memcpy(&(cb0->port_mac_addr), &(mac_addr->sa_data[0]), ETH_ALEN); in ehea_set_mac_addr()
1737 cb0->port_mac_addr = cb0->port_mac_addr >> 16; in ehea_set_mac_addr()
1741 EHEA_BMASK_SET(H_PORT_CB0_MAC, 1), cb0); in ehea_set_mac_addr()
1756 port->mac_addr = cb0->port_mac_addr << 16; in ehea_set_mac_addr()
1770 free_page((unsigned long)cb0); in ehea_set_mac_addr()
2171 struct hcp_modify_qp_cb0 *cb0; in ehea_activate_qp() local
2173 cb0 = (void *)get_zeroed_page(GFP_KERNEL); in ehea_activate_qp()
2174 if (!cb0) { in ehea_activate_qp()
2180 EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0); in ehea_activate_qp()
2186 cb0->qp_ctl_reg = H_QP_CR_STATE_INITIALIZED; in ehea_activate_qp()
2188 EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0, in ehea_activate_qp()
2196 EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0); in ehea_activate_qp()
2202 cb0->qp_ctl_reg = H_QP_CR_ENABLED | H_QP_CR_STATE_INITIALIZED; in ehea_activate_qp()
2204 EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0, in ehea_activate_qp()
2212 EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0); in ehea_activate_qp()
2218 cb0->qp_ctl_reg = H_QP_CR_ENABLED | H_QP_CR_STATE_RDY2SND; in ehea_activate_qp()
2220 EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0, in ehea_activate_qp()
2228 EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0); in ehea_activate_qp()
2236 free_page((unsigned long)cb0); in ehea_activate_qp()
2513 struct hcp_modify_qp_cb0 *cb0; in ehea_stop_qps() local
2521 cb0 = (void *)get_zeroed_page(GFP_KERNEL); in ehea_stop_qps()
2522 if (!cb0) { in ehea_stop_qps()
2537 cb0); in ehea_stop_qps()
2543 cb0->qp_ctl_reg = (cb0->qp_ctl_reg & H_QP_CR_RES_STATE) << 8; in ehea_stop_qps()
2544 cb0->qp_ctl_reg &= ~H_QP_CR_ENABLED; in ehea_stop_qps()
2548 1), cb0, &dummy64, in ehea_stop_qps()
2557 cb0); in ehea_stop_qps()
2573 free_page((unsigned long)cb0); in ehea_stop_qps()
2618 struct hcp_modify_qp_cb0 *cb0; in ehea_restart_qps() local
2623 cb0 = (void *)get_zeroed_page(GFP_KERNEL); in ehea_restart_qps()
2624 if (!cb0) in ehea_restart_qps()
2642 cb0); in ehea_restart_qps()
2649 cb0->qp_ctl_reg = (cb0->qp_ctl_reg & H_QP_CR_RES_STATE) << 8; in ehea_restart_qps()
2650 cb0->qp_ctl_reg |= H_QP_CR_ENABLED; in ehea_restart_qps()
2654 1), cb0, &dummy64, in ehea_restart_qps()
2664 cb0); in ehea_restart_qps()
2677 free_page((unsigned long)cb0); in ehea_restart_qps()