Lines Matching +full:0 +full:- +full:mdio
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
23 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
38 u8 __iomem *vbase; /* mdio reg base address */
43 /* mdio reg */
44 #define MDIO_COMMAND_REG 0x0
45 #define MDIO_ADDR_REG 0x4
46 #define MDIO_WDATA_REG 0x8
47 #define MDIO_RDATA_REG 0xc
48 #define MDIO_STA_REG 0x10
51 #define MDIO_CMD_DEVAD_M 0x1f
52 #define MDIO_CMD_DEVAD_S 0
53 #define MDIO_CMD_PRTAD_M 0x1f
59 #define MDIO_ADDR_DATA_M 0xffff
60 #define MDIO_ADDR_DATA_S 0
62 #define MDIO_WDATA_DATA_M 0xffff
63 #define MDIO_WDATA_DATA_S 0
65 #define MDIO_RDATA_DATA_M 0xffff
66 #define MDIO_RDATA_DATA_S 0
68 #define MDIO_STATE_STA_B 0
71 MDIO_ST_CLAUSE_45 = 0,
81 MDIO_C45_WRITE_ADDR = 0,
88 #define MDIO_SC_CLK_EN 0x338
89 #define MDIO_SC_CLK_DIS 0x33C
90 #define MDIO_SC_RESET_REQ 0xA38
91 #define MDIO_SC_RESET_DREQ 0xA3C
92 #define MDIO_SC_CLK_ST 0x531C
93 #define MDIO_SC_RESET_ST 0x5A1C
101 mdio_write_reg((a)->vbase, (reg), (value))
112 } while (0)
126 mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
137 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
140 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
143 #define MDIO_CHECK_CLR_ST 0
153 regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val); in mdio_sc_cfg_reg_write()
155 for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) { in mdio_sc_cfg_reg_write()
156 ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, ®_value); in mdio_sc_cfg_reg_write()
166 return -EBUSY; in mdio_sc_cfg_reg_write()
168 return 0; in mdio_sc_cfg_reg_write()
173 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_wait_ready()
177 /* waiting for MDIO_COMMAND_REG's mdio_start==0 */ in hns_mdio_wait_ready()
179 for (i = 0; i < MDIO_TIMEOUT; i++) { in hns_mdio_wait_ready()
187 return -ETIMEDOUT; in hns_mdio_wait_ready()
189 return 0; in hns_mdio_wait_ready()
209 * hns_mdio_write_c22 - access phy register
210 * @bus: mdio bus
215 * Return 0 on success, negative on failure
220 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_write_c22()
221 u16 reg = (u16)(regnum & 0xffff); in hns_mdio_write_c22()
226 dev_dbg(&bus->dev, "mdio write %s,base is %p\n", in hns_mdio_write_c22()
227 bus->id, mdio_dev->vbase); in hns_mdio_write_c22()
228 dev_dbg(&bus->dev, "phy id=%d, reg=%#x, write data=%d\n", in hns_mdio_write_c22()
234 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c22()
246 return 0; in hns_mdio_write_c22()
250 * hns_mdio_write_c45 - access phy register
251 * @bus: mdio bus
257 * Return 0 on success, negative on failure
262 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_write_c45()
263 u16 reg = (u16)(regnum & 0xffff); in hns_mdio_write_c45()
268 dev_dbg(&bus->dev, "mdio write %s,base is %p\n", in hns_mdio_write_c45()
269 bus->id, mdio_dev->vbase); in hns_mdio_write_c45()
270 dev_dbg(&bus->dev, "phy id=%d, devad=%d, reg=%#x, write data=%d\n", in hns_mdio_write_c45()
276 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c45()
280 /* config the cmd-reg to write addr*/ in hns_mdio_write_c45()
289 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c45()
302 return 0; in hns_mdio_write_c45()
306 * hns_mdio_read_c22 - access phy register
307 * @bus: mdio bus
315 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_read_c22()
316 u16 reg = (u16)(regnum & 0xffff); in hns_mdio_read_c22()
320 dev_dbg(&bus->dev, "mdio read %s,base is %p\n", in hns_mdio_read_c22()
321 bus->id, mdio_dev->vbase); in hns_mdio_read_c22()
322 dev_dbg(&bus->dev, "phy id=%d, reg=%#x!\n", phy_id, reg); in hns_mdio_read_c22()
327 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_read_c22()
333 /* Step 2: waiting for MDIO_COMMAND_REG 's mdio_start==0,*/ in hns_mdio_read_c22()
337 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_read_c22()
343 dev_err(&bus->dev, " ERROR! MDIO Read failed!\n"); in hns_mdio_read_c22()
344 return -EBUSY; in hns_mdio_read_c22()
355 * hns_mdio_read_c45 - access phy register
356 * @bus: mdio bus
366 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_read_c45()
367 u16 reg = (u16)(regnum & 0xffff); in hns_mdio_read_c45()
371 dev_dbg(&bus->dev, "mdio read %s,base is %p\n", in hns_mdio_read_c45()
372 bus->id, mdio_dev->vbase); in hns_mdio_read_c45()
373 dev_dbg(&bus->dev, "phy id=%d, devad=%d, reg=%#x!\n", in hns_mdio_read_c45()
379 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_read_c45()
386 /* Step 2; config the cmd-reg to write addr*/ in hns_mdio_read_c45()
392 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_read_c45()
398 /* Step 5: waiting for MDIO_COMMAND_REG 's mdio_start==0,*/ in hns_mdio_read_c45()
402 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_read_c45()
408 dev_err(&bus->dev, " ERROR! MDIO Read failed!\n"); in hns_mdio_read_c45()
409 return -EBUSY; in hns_mdio_read_c45()
420 * hns_mdio_reset - reset mdio bus
421 * @bus: mdio bus
423 * Return 0 on success, negative on failure
427 struct hns_mdio_device *mdio_dev = bus->priv; in hns_mdio_reset()
431 if (dev_of_node(bus->parent)) { in hns_mdio_reset()
432 if (!mdio_dev->subctrl_vbase) { in hns_mdio_reset()
433 dev_err(&bus->dev, "mdio sys ctl reg has not mapped\n"); in hns_mdio_reset()
434 return -ENODEV; in hns_mdio_reset()
437 sc_reg = &mdio_dev->sc_reg; in hns_mdio_reset()
439 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req, in hns_mdio_reset()
440 0x1, sc_reg->mdio_reset_st, 0x1, in hns_mdio_reset()
443 dev_err(&bus->dev, "MDIO reset fail\n"); in hns_mdio_reset()
448 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis, in hns_mdio_reset()
449 0x1, sc_reg->mdio_clk_st, 0x1, in hns_mdio_reset()
452 dev_err(&bus->dev, "MDIO dis clk fail\n"); in hns_mdio_reset()
457 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq, in hns_mdio_reset()
458 0x1, sc_reg->mdio_reset_st, 0x1, in hns_mdio_reset()
461 dev_err(&bus->dev, "MDIO dis clk fail\n"); in hns_mdio_reset()
466 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en, in hns_mdio_reset()
467 0x1, sc_reg->mdio_clk_st, 0x1, in hns_mdio_reset()
470 dev_err(&bus->dev, "MDIO en clk fail\n"); in hns_mdio_reset()
471 } else if (is_acpi_node(bus->parent->fwnode)) { in hns_mdio_reset()
474 s = acpi_evaluate_object(ACPI_HANDLE(bus->parent), in hns_mdio_reset()
477 dev_err(&bus->dev, "Reset failed, return:%#x\n", s); in hns_mdio_reset()
478 ret = -EBUSY; in hns_mdio_reset()
480 ret = 0; in hns_mdio_reset()
483 dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n"); in hns_mdio_reset()
484 ret = -ENXIO; in hns_mdio_reset()
490 * hns_mdio_probe - probe mdio device
491 * @pdev: mdio platform device
493 * Return 0 on success, negative on failure
503 return -ENODEV; in hns_mdio_probe()
506 mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL); in hns_mdio_probe()
508 return -ENOMEM; in hns_mdio_probe()
510 new_bus = devm_mdiobus_alloc(&pdev->dev); in hns_mdio_probe()
512 dev_err(&pdev->dev, "mdiobus_alloc fail!\n"); in hns_mdio_probe()
513 return -ENOMEM; in hns_mdio_probe()
516 new_bus->name = MDIO_BUS_NAME; in hns_mdio_probe()
517 new_bus->read = hns_mdio_read_c22; in hns_mdio_probe()
518 new_bus->write = hns_mdio_write_c22; in hns_mdio_probe()
519 new_bus->read_c45 = hns_mdio_read_c45; in hns_mdio_probe()
520 new_bus->write_c45 = hns_mdio_write_c45; in hns_mdio_probe()
521 new_bus->reset = hns_mdio_reset; in hns_mdio_probe()
522 new_bus->priv = mdio_dev; in hns_mdio_probe()
523 new_bus->parent = &pdev->dev; in hns_mdio_probe()
525 mdio_dev->vbase = devm_platform_ioremap_resource(pdev, 0); in hns_mdio_probe()
526 if (IS_ERR(mdio_dev->vbase)) { in hns_mdio_probe()
527 ret = PTR_ERR(mdio_dev->vbase); in hns_mdio_probe()
532 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii", in hns_mdio_probe()
533 dev_name(&pdev->dev)); in hns_mdio_probe()
534 if (dev_of_node(&pdev->dev)) { in hns_mdio_probe()
537 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, in hns_mdio_probe()
538 "subctrl-vbase", in hns_mdio_probe()
540 0, in hns_mdio_probe()
543 mdio_dev->subctrl_vbase = in hns_mdio_probe()
545 if (IS_ERR(mdio_dev->subctrl_vbase)) { in hns_mdio_probe()
546 dev_warn(&pdev->dev, "syscon_node_to_regmap error\n"); in hns_mdio_probe()
547 mdio_dev->subctrl_vbase = NULL; in hns_mdio_probe()
550 mdio_dev->sc_reg.mdio_clk_en = in hns_mdio_probe()
551 (u16)reg_args.args[0]; in hns_mdio_probe()
552 mdio_dev->sc_reg.mdio_clk_dis = in hns_mdio_probe()
553 (u16)reg_args.args[0] + 4; in hns_mdio_probe()
554 mdio_dev->sc_reg.mdio_reset_req = in hns_mdio_probe()
556 mdio_dev->sc_reg.mdio_reset_dreq = in hns_mdio_probe()
558 mdio_dev->sc_reg.mdio_clk_st = in hns_mdio_probe()
560 mdio_dev->sc_reg.mdio_reset_st = in hns_mdio_probe()
564 mdio_dev->sc_reg.mdio_clk_en = in hns_mdio_probe()
566 mdio_dev->sc_reg.mdio_clk_dis = in hns_mdio_probe()
568 mdio_dev->sc_reg.mdio_reset_req = in hns_mdio_probe()
570 mdio_dev->sc_reg.mdio_reset_dreq = in hns_mdio_probe()
572 mdio_dev->sc_reg.mdio_clk_st = in hns_mdio_probe()
574 mdio_dev->sc_reg.mdio_reset_st = in hns_mdio_probe()
580 dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret); in hns_mdio_probe()
581 mdio_dev->subctrl_vbase = NULL; in hns_mdio_probe()
584 ret = of_mdiobus_register(new_bus, pdev->dev.of_node); in hns_mdio_probe()
585 } else if (is_acpi_node(pdev->dev.fwnode)) { in hns_mdio_probe()
587 memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR); in hns_mdio_probe()
590 new_bus->phy_mask = ~0; in hns_mdio_probe()
592 /* Register the MDIO bus */ in hns_mdio_probe()
595 dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n"); in hns_mdio_probe()
596 ret = -ENXIO; in hns_mdio_probe()
600 dev_err(&pdev->dev, "Cannot register as MDIO bus!\n"); in hns_mdio_probe()
605 return 0; in hns_mdio_probe()
609 * hns_mdio_remove - remove mdio device
610 * @pdev: mdio platform device
612 * Return 0 on success, negative on failure
625 {.compatible = "hisilicon,mdio"},
626 {.compatible = "hisilicon,hns-mdio"},
632 { "HISI0141", 0 },
651 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");