527 	if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)  in hclge_tm_pg_schd_mode_cfg()
724 	vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;  in hclge_tm_vport_tc_info_update()
768 			bw_limit = hdev->tm_info.pg_info[0].bw_limit;  in hclge_tm_tc_info_init()
797 		hdev->tm_info.pg_info[i].pg_id = i;  in hclge_tm_pg_info_init()
798 		hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;  in hclge_tm_pg_info_init()
800 		hdev->tm_info.pg_info[i].bw_limit =  in hclge_tm_pg_info_init()
806 		hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;  in hclge_tm_pg_info_init()
808 			hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;  in hclge_tm_pg_info_init()
810 			hdev->tm_info.pg_info[i].tc_dwrr[k] = DEFAULT_BW_WEIGHT;  in hclge_tm_pg_info_init()
875 			hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);  in hclge_tm_pg_to_pri_map()
897 		u32 rate = hdev->tm_info.pg_info[i].bw_limit;  in hclge_tm_pg_shaper_cfg()
1186 	struct hclge_pg_info *pg_info;  in hclge_tm_pri_tc_base_dwrr_cfg()  local
1192 		pg_info =  in hclge_tm_pri_tc_base_dwrr_cfg()
1193 			&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];  in hclge_tm_pri_tc_base_dwrr_cfg()
1194 		dwrr = pg_info->tc_dwrr[i];  in hclge_tm_pri_tc_base_dwrr_cfg()
1230 		struct hclge_pg_info *pg_info;  in hclge_tm_ets_tc_dwrr_cfg()  local
1232 		pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];  in hclge_tm_ets_tc_dwrr_cfg()
1233 		ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];  in hclge_tm_ets_tc_dwrr_cfg()
1257 			hdev->tm_info.pg_info[0].tc_dwrr[i]);  in hclge_tm_pri_vnet_base_dwrr_pri_cfg()