Lines Matching +full:0 +full:x29000

14 #define HCLGE_PTP_REG_OFFSET	0x29000
16 #define HCLGE_PTP_TX_TS_SEQID_REG	0x0
17 #define HCLGE_PTP_TX_TS_NSEC_REG	0x4
18 #define HCLGE_PTP_TX_TS_NSEC_MASK	GENMASK(29, 0)
19 #define HCLGE_PTP_TX_TS_SEC_L_REG	0x8
20 #define HCLGE_PTP_TX_TS_SEC_H_REG	0xC
21 #define HCLGE_PTP_TX_TS_SEC_H_MASK	GENMASK(15, 0)
22 #define HCLGE_PTP_TX_TS_CNT_REG		0x30
24 #define HCLGE_PTP_TIME_SEC_H_REG	0x50
25 #define HCLGE_PTP_TIME_SEC_H_MASK	GENMASK(15, 0)
26 #define HCLGE_PTP_TIME_SEC_L_REG	0x54
27 #define HCLGE_PTP_TIME_NSEC_REG		0x58
28 #define HCLGE_PTP_TIME_NSEC_MASK	GENMASK(29, 0)
30 #define HCLGE_PTP_TIME_SYNC_REG		0x5C
31 #define HCLGE_PTP_TIME_SYNC_EN		BIT(0)
32 #define HCLGE_PTP_TIME_ADJ_REG		0x60
33 #define HCLGE_PTP_TIME_ADJ_EN		BIT(0)
34 #define HCLGE_PTP_CYCLE_QUO_REG		0x64
35 #define HCLGE_PTP_CYCLE_QUO_MASK	GENMASK(7, 0)
36 #define HCLGE_PTP_CYCLE_DEN_REG		0x68
37 #define HCLGE_PTP_CYCLE_NUM_REG		0x6C
38 #define HCLGE_PTP_CYCLE_CFG_REG		0x70
39 #define HCLGE_PTP_CYCLE_ADJ_EN		BIT(0)
40 #define HCLGE_PTP_CUR_TIME_SEC_H_REG	0x74
41 #define HCLGE_PTP_CUR_TIME_SEC_L_REG	0x78
42 #define HCLGE_PTP_CUR_TIME_NSEC_REG	0x7C
46 #define HCLGE_PTP_SEC_L_MASK		GENMASK(31, 0)
48 #define HCLGE_PTP_FLAG_EN		0
80 #define HCLGE_PTP_INT_EN_B	BIT(0)
103 	HCLGE_PTP_MSG0_V2_EVENT = 0xF,
109 #define HCLGE_PTP_EN_B			BIT(0)