1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
46 	struct hclge_dev *hdev = bus->priv;  in hclge_mdio_write()
50 	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))  in hclge_mdio_write()
51 		return -EBUSY;  in hclge_mdio_write()
57 	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,  in hclge_mdio_write()
59 	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,  in hclge_mdio_write()
62 	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);  in hclge_mdio_write()
63 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,  in hclge_mdio_write()
65 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,  in hclge_mdio_write()
68 	mdio_cmd->data_wr = cpu_to_le16(data);  in hclge_mdio_write()
70 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);  in hclge_mdio_write()
72 		dev_err(&hdev->pdev->dev,  in hclge_mdio_write()
84 	struct hclge_dev *hdev = bus->priv;  in hclge_mdio_read()
88 	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))  in hclge_mdio_read()
89 		return -EBUSY;  in hclge_mdio_read()
95 	hnae3_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,  in hclge_mdio_read()
97 	hnae3_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,  in hclge_mdio_read()
100 	hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);  in hclge_mdio_read()
101 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,  in hclge_mdio_read()
103 	hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,  in hclge_mdio_read()
107 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);  in hclge_mdio_read()
109 		dev_err(&hdev->pdev->dev,  in hclge_mdio_read()
115 	if (hnae3_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) {  in hclge_mdio_read()
116 		dev_err(&hdev->pdev->dev, "mdio read data error\n");  in hclge_mdio_read()
117 		return -EIO;  in hclge_mdio_read()
120 	return le16_to_cpu(mdio_cmd->data_rd);  in hclge_mdio_read()
127 	struct hclge_mac *mac = &hdev->hw.mac;  in hclge_mac_mdio_config()
132 	if (hdev->hw.mac.phy_addr == PHY_INEXISTENT) {  in hclge_mac_mdio_config()
133 		dev_info(&hdev->pdev->dev,  in hclge_mac_mdio_config()
136 	} else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) {  in hclge_mac_mdio_config()
137 		dev_err(&hdev->pdev->dev, "phy_addr(%u) is too large.\n",  in hclge_mac_mdio_config()
138 			hdev->hw.mac.phy_addr);  in hclge_mac_mdio_config()
139 		return -EINVAL;  in hclge_mac_mdio_config()
142 	mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev);  in hclge_mac_mdio_config()
144 		return -ENOMEM;  in hclge_mac_mdio_config()
146 	mdio_bus->name = "hisilicon MII bus";  in hclge_mac_mdio_config()
147 	mdio_bus->read = hclge_mdio_read;  in hclge_mac_mdio_config()
148 	mdio_bus->write = hclge_mdio_write;  in hclge_mac_mdio_config()
149 	snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii",  in hclge_mac_mdio_config()
150 		 dev_name(&hdev->pdev->dev));  in hclge_mac_mdio_config()
152 	mdio_bus->parent = &hdev->pdev->dev;  in hclge_mac_mdio_config()
153 	mdio_bus->priv = hdev;  in hclge_mac_mdio_config()
154 	mdio_bus->phy_mask = ~(1 << mac->phy_addr);  in hclge_mac_mdio_config()
157 		dev_err(mdio_bus->parent,  in hclge_mac_mdio_config()
162 	phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr);  in hclge_mac_mdio_config()
164 		dev_err(mdio_bus->parent, "Failed to get phy device\n");  in hclge_mac_mdio_config()
166 		return -EIO;  in hclge_mac_mdio_config()
169 	mac->phydev = phydev;  in hclge_mac_mdio_config()
170 	mac->mdio_bus = mdio_bus;  in hclge_mac_mdio_config()
179 	struct hclge_dev *hdev = vport->back;  in hclge_mac_adjust_link()
184 	if (netdev->phydev->link == 0)  in hclge_mac_adjust_link()
187 	speed = netdev->phydev->speed;  in hclge_mac_adjust_link()
188 	duplex = netdev->phydev->duplex;  in hclge_mac_adjust_link()
194 	hdev->hw.mac.req_speed = (u32)speed;  in hclge_mac_adjust_link()
195 	hdev->hw.mac.req_duplex = (u8)duplex;  in hclge_mac_adjust_link()
205 	struct hclge_dev *hdev = vport->back;  in hclge_mac_connect_phy()
206 	struct net_device *netdev = hdev->vport[0].nic.netdev;  in hclge_mac_connect_phy()
207 	struct phy_device *phydev = hdev->hw.mac.phydev;  in hclge_mac_connect_phy()
214 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);  in hclge_mac_connect_phy()
216 	phydev->dev_flags |= MARVELL_PHY_LED0_LINK_LED1_ACTIVE;  in hclge_mac_connect_phy()
226 	linkmode_copy(mask, hdev->hw.mac.supported);  in hclge_mac_connect_phy()
227 	linkmode_and(phydev->supported, phydev->supported, mask);  in hclge_mac_connect_phy()
228 	linkmode_copy(phydev->advertising, phydev->supported);  in hclge_mac_connect_phy()
230 	/* supported flag is Pause and Asym Pause, but default advertising  in hclge_mac_connect_phy()
231 	 * should be rx on, tx on, so need clear Asym Pause in advertising  in hclge_mac_connect_phy()
235 			   phydev->advertising);  in hclge_mac_connect_phy()
245 	struct hclge_dev *hdev = vport->back;  in hclge_mac_disconnect_phy()
246 	struct phy_device *phydev = hdev->hw.mac.phydev;  in hclge_mac_disconnect_phy()
256 	struct phy_device *phydev = hdev->hw.mac.phydev;  in hclge_mac_start_phy()
268 	struct net_device *netdev = hdev->vport[0].nic.netdev;  in hclge_mac_stop_phy()
269 	struct phy_device *phydev = netdev->phydev;  in hclge_mac_stop_phy()
286 	req->reg_addr = cpu_to_le16(reg_addr);  in hclge_read_phy_reg()
288 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);  in hclge_read_phy_reg()
290 		dev_err(&hdev->pdev->dev,  in hclge_read_phy_reg()
293 	return le16_to_cpu(req->reg_val);  in hclge_read_phy_reg()
305 	req->reg_addr = cpu_to_le16(reg_addr);  in hclge_write_phy_reg()
306 	req->reg_val = cpu_to_le16(val);  in hclge_write_phy_reg()
308 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);  in hclge_write_phy_reg()
310 		dev_err(&hdev->pdev->dev,  in hclge_write_phy_reg()