Lines Matching +full:0 +full:x0f000000
16 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
17 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
18 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
22 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
24 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
25 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
26 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
27 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
28 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
29 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
30 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
31 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
32 #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
33 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
34 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
35 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
36 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
37 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
38 #define HCLGE_IGU_ERR_INT_EN 0x0000000F
39 #define HCLGE_IGU_ERR_INT_TYPE 0x00000660
40 #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
41 #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
42 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
43 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
44 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
45 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
46 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
47 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003
48 #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
49 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
50 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
51 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
52 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
53 #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
54 #define HCLGE_TM_QCN_ERR_INT_TYPE 0x29
55 #define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF00
56 #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
57 #define HCLGE_NCSI_ERR_INT_EN 0x3
58 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
59 #define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
60 #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
61 #define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
62 #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
63 #define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
64 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
65 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
66 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
67 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
68 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
69 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
70 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
71 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
72 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
74 #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
75 #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
76 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
77 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
78 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
79 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
80 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
81 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
82 #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
83 #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
84 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
85 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
86 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
87 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
89 #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
90 #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
91 #define HCLGE_IGU_INT_MASK GENMASK(3, 0)
92 #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
93 #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
94 #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
96 #define HCLGE_PPU_PF_INT_RAS_MASK 0x18
97 #define HCLGE_PPU_PF_INT_MSIX_MASK 0x26
98 #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01
99 #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
100 #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
101 #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
103 #define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
104 #define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
105 #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
106 #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
107 #define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
109 #define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)
112 #define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
113 #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
132 HCLGE_ERR_INT_MSIX = 0,
139 MODULE_NONE = 0,
170 NONE_ERROR = 0,