Lines Matching +full:0 +full:x90
35 { "HISI00B1", 0 },
36 { "HISI00B2", 0 },
46 u32 reset_offset = 0; in hns_dsaf_get_cfg()
47 u32 res_idx = 0; in hns_dsaf_get_cfg()
60 if (acpi_dev_found(hns_dsaf_acpi_match[0].id)) in hns_dsaf_get_cfg()
76 for (i = 0; i < DSAF_MODE_MAX; i++) { in hns_dsaf_get_cfg()
102 np_temp = of_parse_phandle(np, "subctrl-syscon", 0); in hns_dsaf_get_cfg()
165 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT || in hns_dsaf_get_cfg()
175 if (ret < 0) { in hns_dsaf_get_cfg()
182 if (ret < 0) { in hns_dsaf_get_cfg()
190 if (dsaf_dev->buf_size_type < 0) { in hns_dsaf_get_cfg()
205 return 0; in hns_dsaf_get_cfg()
239 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_ppe_qid_cfg()
241 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i, in hns_dsaf_ppe_qid_cfg()
256 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) { in hns_dsaf_mix_def_qid_cfg()
258 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i, in hns_dsaf_mix_def_qid_cfg()
259 0xff, 0, q_id); in hns_dsaf_mix_def_qid_cfg()
276 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) { in hns_dsaf_inner_qid_cfg()
296 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { in hns_dsaf_sw_port_type_cfg()
298 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i, in hns_dsaf_sw_port_type_cfg()
314 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_stp_port_type_cfg()
316 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i, in hns_dsaf_stp_port_type_cfg()
333 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { in hns_dsaf_sbm_cfg()
335 DSAF_SBM_CFG_REG_0_REG + 0x80 * i); in hns_dsaf_sbm_cfg()
337 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0); in hns_dsaf_sbm_cfg()
339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg); in hns_dsaf_sbm_cfg()
354 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */ in hns_dsaf_sbm_cfg_mib_en()
355 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { in hns_dsaf_sbm_cfg_mib_en()
356 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_cfg_mib_en()
357 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); in hns_dsaf_sbm_cfg_mib_en()
360 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { in hns_dsaf_sbm_cfg_mib_en()
361 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_cfg_mib_en()
366 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { in hns_dsaf_sbm_cfg_mib_en()
367 read_cnt = 0; in hns_dsaf_sbm_cfg_mib_en()
368 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_cfg_mib_en()
374 } while (sbm_cfg_mib_en == 0 && in hns_dsaf_sbm_cfg_mib_en()
377 if (sbm_cfg_mib_en == 0) { in hns_dsaf_sbm_cfg_mib_en()
385 return 0; in hns_dsaf_sbm_cfg_mib_en()
399 for (i = 0; i < DSAF_XGE_NUM; i++) { in hns_dsaf_sbm_bp_wl_cfg()
400 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
405 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); in hns_dsaf_sbm_bp_wl_cfg()
407 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); in hns_dsaf_sbm_bp_wl_cfg()
410 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
413 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); in hns_dsaf_sbm_bp_wl_cfg()
415 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); in hns_dsaf_sbm_bp_wl_cfg()
418 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
426 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
437 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
449 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_sbm_bp_wl_cfg()
450 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
460 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_sbm_bp_wl_cfg()
461 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; in hns_dsaf_sbm_bp_wl_cfg()
478 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) { in hns_dsafv2_sbm_bp_wl_cfg()
479 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
484 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); in hns_dsafv2_sbm_bp_wl_cfg()
486 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); in hns_dsafv2_sbm_bp_wl_cfg()
489 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
492 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); in hns_dsafv2_sbm_bp_wl_cfg()
494 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); in hns_dsafv2_sbm_bp_wl_cfg()
497 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
505 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
516 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
528 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) { in hns_dsafv2_sbm_bp_wl_cfg()
529 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
544 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) { in hns_dsafv2_sbm_bp_wl_cfg()
545 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; in hns_dsafv2_sbm_bp_wl_cfg()
566 for (i = 0; i < DSAF_VOQ_NUM; i++) { in hns_dsaf_voq_bp_all_thrd_cfg()
568 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i); in hns_dsaf_voq_bp_all_thrd_cfg()
585 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i, in hns_dsaf_voq_bp_all_thrd_cfg()
646 mcast->tbl_mcast_port_msk[0]); in hns_dsaf_tbl_tcam_mcast_cfg()
707 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); in hns_dsaf_tbl_tcam_mcast_pul()
722 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0); in hns_dsaf_tbl_line_pul()
739 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); in hns_dsaf_tbl_tcam_data_mcast_pul()
740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); in hns_dsaf_tbl_tcam_data_mcast_pul()
757 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); in hns_dsaf_tbl_tcam_data_ucast_pul()
758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0); in hns_dsaf_tbl_tcam_data_ucast_pul()
801 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set); in hns_dsaf_int_xge_msk_set()
808 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set); in hns_dsaf_int_ppe_msk_set()
815 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set); in hns_dsaf_int_rocee_msk_set()
829 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src); in hns_dsaf_int_xge_src_clr()
836 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src); in hns_dsaf_int_ppe_src_clr()
843 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src); in hns_dsaf_int_rocee_src_clr()
956 tcam_mask->tbl_tcam_data_high = 0xffffffff; in hns_dsaf_tcam_uc_cfg_vague()
957 tcam_mask->tbl_tcam_data_low = 0xffffffff; in hns_dsaf_tcam_uc_cfg_vague()
985 tcam_mask->tbl_tcam_data_high = 0xffffffff; in hns_dsaf_tcam_mc_cfg_vague()
986 tcam_mask->tbl_tcam_data_low = 0xffffffff; in hns_dsaf_tcam_mc_cfg_vague()
1005 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0); in hns_dsaf_tcam_mc_invld()
1006 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0); in hns_dsaf_tcam_mc_invld()
1007 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0); in hns_dsaf_tcam_mc_invld()
1008 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0); in hns_dsaf_tcam_mc_invld()
1009 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0); in hns_dsaf_tcam_mc_invld()
1020 addr[0] = mac_key->high.bits.mac_0; in hns_dsaf_tcam_addr_get()
1110 ptbl_tcam_mcast->tbl_mcast_port_msk[0] = in hns_dsaf_tcam_mc_get()
1139 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} }; in hns_dsaf_tbl_line_init()
1141 for (i = 0; i < DSAF_LINE_SUM; i++) in hns_dsaf_tbl_line_init()
1152 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} }; in hns_dsaf_tbl_tcam_init()
1153 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} }; in hns_dsaf_tbl_tcam_init()
1156 for (i = 0; i < DSAF_TCAM_SUM; i++) in hns_dsaf_tbl_tcam_init()
1201 return 0; in hns_dsaf_set_rx_mac_pause_en()
1228 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0); in hns_dsaf_comm_init()
1229 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0); in hns_dsaf_comm_init()
1230 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0); in hns_dsaf_comm_init()
1248 /*set dsaf pfc to 0 for parseing rx pause*/ in hns_dsaf_comm_init()
1249 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_comm_init()
1250 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0); in hns_dsaf_comm_init()
1255 for (i = 0; i < DSAF_COMM_CHN; i++) { in hns_dsaf_comm_init()
1256 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1257 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1258 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1260 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1261 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1262 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful); in hns_dsaf_comm_init()
1264 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful); in hns_dsaf_comm_init()
1265 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful); in hns_dsaf_comm_init()
1284 for (i = 0; i < DSAF_INODE_NUM; i++) { in hns_dsaf_inode_init()
1285 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; in hns_dsaf_inode_init()
1292 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) { in hns_dsaf_inode_init()
1293 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; in hns_dsaf_inode_init()
1296 DSAF_INODE_IN_PORT_NUM_S, 0); in hns_dsaf_inode_init()
1314 for (i = 0; i < DSAF_INODE_NUM; i++) { in hns_dsaf_inode_init()
1315 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; in hns_dsaf_inode_init()
1328 u32 cnt = 0; in hns_dsaf_sbm_init()
1371 return 0; in hns_dsaf_sbm_init()
1406 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); in hns_dsaf_init_hw()
1426 return 0; in hns_dsaf_init_hw()
1436 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); in hns_dsaf_remove_hw()
1442 * return 0 - success , negative --fail
1452 return 0; in hns_dsaf_init()
1474 for (i = 0; i < DSAF_TCAM_SUM; i++) in hns_dsaf_init()
1477 return 0; in hns_dsaf_init()
1515 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { in hns_dsaf_find_soft_mac_entry()
1540 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { in hns_dsaf_find_empty_mac_entry()
1563 for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) { in hns_dsaf_find_empty_mac_entry_reverse()
1588 /*DSAF mode : in port id fixed 0*/ in hns_dsaf_set_mac_key()
1589 port = 0; in hns_dsaf_set_mac_key()
1594 mac_key->high.bits.mac_0 = addr[0]; in hns_dsaf_set_mac_key()
1600 mac_key->low.bits.port_vlan = 0; in hns_dsaf_set_mac_key()
1659 mac_data.tbl_ucast_mac_discard = 0; in hns_dsaf_set_mac_uc_entry()
1660 mac_data.tbl_ucast_old_en = 0; in hns_dsaf_set_mac_uc_entry()
1661 /* default config dvc to 0 */ in hns_dsaf_set_mac_uc_entry()
1662 mac_data.tbl_ucast_dvc = 0; in hns_dsaf_set_mac_uc_entry()
1675 return 0; in hns_dsaf_set_mac_uc_entry()
1699 /* can not find the tcam entry, return 0 */ in hns_dsaf_rm_mac_addr()
1704 return 0; in hns_dsaf_rm_mac_addr()
1741 a[0] &= b[0]; in hns_dsaf_mc_mask_bit_clear()
1783 0x0, in hns_dsaf_add_mac_mc_port()
1784 0xff, in hns_dsaf_add_mac_mc_port()
1795 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg)); in hns_dsaf_add_mac_mc_port()
1830 mac_data.tbl_mcast_old_en = 0; in hns_dsaf_add_mac_mc_port()
1851 return 0; in hns_dsaf_add_mac_mc_port()
1902 return 0; in hns_dsaf_del_mac_entry()
1922 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0}; in hns_dsaf_del_mac_mc_port()
1952 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask); in hns_dsaf_del_mac_mc_port()
1996 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0); in hns_dsaf_del_mac_mc_port()
2015 return 0; in hns_dsaf_del_mac_mc_port()
2024 int ret = 0, i; in hns_dsaf_clr_mac_mc_port()
2027 return 0; in hns_dsaf_clr_mac_mc_port()
2029 for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) { in hns_dsaf_clr_mac_mc_port()
2045 const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0}; in hns_dsaf_clr_mac_mc_port()
2071 mac_id % 32, 0); in hns_dsaf_clr_mac_mc_port()
2139 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id), in hns_dsaf_pfc_unit_cnt()
2157 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id); in hns_dsaf_port_work_rate_cfg()
2162 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0); in hns_dsaf_port_work_rate_cfg()
2165 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id, in hns_dsaf_port_work_rate_cfg()
2212 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2214 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2216 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2218 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2223 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2226 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2228 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2230 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2232 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2234 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2236 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num); in hns_dsaf_update_stats()
2245 for (i = 0; i < DSAF_PRIO_NR; i++) { in hns_dsaf_update_stats()
2248 reg_tmp + 0x4 * (u64)node_num); in hns_dsaf_update_stats()
2252 0xF0 * (u64)node_num); in hns_dsaf_update_stats()
2256 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num); in hns_dsaf_update_stats()
2274 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG); in hns_dsaf_get_regs()
2300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) in hns_dsaf_get_regs()
2306 for (i = 0; i < DSAF_SW_PORT_NUM; i++) in hns_dsaf_get_regs()
2310 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) in hns_dsaf_get_regs()
2318 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80); in hns_dsaf_get_regs()
2320 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { in hns_dsaf_get_regs()
2323 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2325 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2327 DSAF_INODE_BP_STATUS_0_REG + j * 0x80); in hns_dsaf_get_regs()
2329 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2331 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2333 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2335 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2338 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80); in hns_dsaf_get_regs()
2340 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2342 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2344 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2346 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2348 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2350 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2352 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80); in hns_dsaf_get_regs()
2365 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { in hns_dsaf_get_regs()
2372 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80); in hns_dsaf_get_regs()
2375 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) { in hns_dsaf_get_regs()
2378 DSAF_SBM_CFG_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2380 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2382 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2384 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2386 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80); in hns_dsaf_get_regs()
2388 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80); in hns_dsaf_get_regs()
2390 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80); in hns_dsaf_get_regs()
2392 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80); in hns_dsaf_get_regs()
2394 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80); in hns_dsaf_get_regs()
2396 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80); in hns_dsaf_get_regs()
2398 DSAF_SBM_INER_ST_0_REG + j * 0x80); in hns_dsaf_get_regs()
2400 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80); in hns_dsaf_get_regs()
2402 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2404 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2406 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2408 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2410 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2412 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2414 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2416 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2418 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2420 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2422 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2424 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2426 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80); in hns_dsaf_get_regs()
2428 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2430 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80); in hns_dsaf_get_regs()
2434 for (i = 0; i < DSAF_XOD_NUM; i++) { in hns_dsaf_get_regs()
2436 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2438 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2440 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2442 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2444 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2446 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90); in hns_dsaf_get_regs()
2449 p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90); in hns_dsaf_get_regs()
2450 p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90); in hns_dsaf_get_regs()
2451 p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90); in hns_dsaf_get_regs()
2453 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) { in hns_dsaf_get_regs()
2456 DSAF_XOD_GNT_L_0_REG + j * 0x90); in hns_dsaf_get_regs()
2458 DSAF_XOD_GNT_H_0_REG + j * 0x90); in hns_dsaf_get_regs()
2460 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90); in hns_dsaf_get_regs()
2462 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2464 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2466 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2468 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2470 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2472 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2474 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90); in hns_dsaf_get_regs()
2478 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2480 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2482 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2484 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2486 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2488 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2490 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2492 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2494 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2496 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2498 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2500 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90); in hns_dsaf_get_regs()
2502 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90); in hns_dsaf_get_regs()
2505 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) { in hns_dsaf_get_regs()
2506 j = (i * DSAF_COMM_CHN + port) * 0x90; in hns_dsaf_get_regs()
2555 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { in hns_dsaf_get_regs()
2556 j = i * 0x8; in hns_dsaf_get_regs()
2577 p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4); in hns_dsaf_get_regs()
2578 p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4); in hns_dsaf_get_regs()
2579 p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4); in hns_dsaf_get_regs()
2581 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4); in hns_dsaf_get_regs()
2582 p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4); in hns_dsaf_get_regs()
2583 p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4); in hns_dsaf_get_regs()
2586 p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4); in hns_dsaf_get_regs()
2590 p[i] = 0xdddddddd; in hns_dsaf_get_regs()
2627 for (i = 0; i < DSAF_PRIO_NR; i++) { in hns_dsaf_get_node_stats_strings()
2628 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR, in hns_dsaf_get_node_stats_strings()
2652 p[0] = hw_stats->pad_drop; in hns_dsaf_get_node_stats()
2666 for (i = 0; i < DSAF_PRIO_NR; i++) { in hns_dsaf_get_node_stats()
2667 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i]; in hns_dsaf_get_node_stats()
2713 return 0; in hns_dsaf_get_sset_count()
2762 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80}; in set_promisc_tcam_enable()
2763 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port}; in set_promisc_tcam_enable()
2764 struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf}; in set_promisc_tcam_enable()
2765 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} }; in set_promisc_tcam_enable()
2767 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port}; in set_promisc_tcam_enable()
2774 u8 addr[ETH_ALEN] = {0}; in set_promisc_tcam_enable()
2778 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */ in set_promisc_tcam_enable()
2779 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); in set_promisc_tcam_enable()
2795 (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num); in set_promisc_tcam_enable()
2820 memset(&mask_entry, 0x0, sizeof(mask_entry)); in set_promisc_tcam_enable()
2821 memset(&mask_key, 0x0, sizeof(mask_key)); in set_promisc_tcam_enable()
2822 memset(&temp_key, 0x0, sizeof(temp_key)); in set_promisc_tcam_enable()
2823 mask_entry.addr[0] = 0x01; in set_promisc_tcam_enable()
2825 0xf, mask_entry.addr); in set_promisc_tcam_enable()
2827 tbl_tcam_mcast.tbl_mcast_old_en = 0; in set_promisc_tcam_enable()
2866 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port}; in set_promisc_tcam_disable()
2867 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0}; in set_promisc_tcam_disable()
2868 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} }; in set_promisc_tcam_disable()
2870 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0}; in set_promisc_tcam_disable()
2871 struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0}; in set_promisc_tcam_disable()
2875 u8 addr[ETH_ALEN] = {0}; in set_promisc_tcam_disable()
2878 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */ in set_promisc_tcam_disable()
2879 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); in set_promisc_tcam_disable()
2896 addr[0] = 0x01; in set_promisc_tcam_disable()
2897 memset(&mac_key, 0x0, sizeof(mac_key)); in set_promisc_tcam_disable()
2898 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); in set_promisc_tcam_disable()
2928 return 0; in hns_dsaf_wait_pkt_clean()
2930 wait_cnt = 0; in hns_dsaf_wait_pkt_clean()
2933 (port + DSAF_XGE_NUM) * 0x40); in hns_dsaf_wait_pkt_clean()
2935 (port + DSAF_XGE_NUM) * 0x40); in hns_dsaf_wait_pkt_clean()
2948 return 0; in hns_dsaf_wait_pkt_clean()
2954 * return 0 - success , negative --fail
2989 return 0; in hns_dsaf_probe()
3048 * return 0 - success , negative -fail
3120 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) in hns_dsaf_roce_reset()
3123 dsaf_set_field(mp, 3 << i * 3, i * 3, 0); in hns_dsaf_roce_reset()
3127 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) in hns_dsaf_roce_reset()
3140 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0); in hns_dsaf_roce_reset()
3149 return 0; in hns_dsaf_roce_reset()