Lines Matching +full:mac +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-or-later
189 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
198 #define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
249 void __iomem *base; member
278 if (!priv->mac_ifc_rst) in hix5hd2_mac_interface_reset()
281 reset_control_assert(priv->mac_ifc_rst); in hix5hd2_mac_interface_reset()
282 reset_control_deassert(priv->mac_ifc_rst); in hix5hd2_mac_interface_reset()
290 priv->speed = speed; in hix5hd2_config_port()
291 priv->duplex = duplex; in hix5hd2_config_port()
293 switch (priv->phy_mode) { in hix5hd2_config_port()
316 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
319 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
326 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
327 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
328 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
333 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
334 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
335 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
337 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
338 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
339 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
341 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
342 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); in hix5hd2_set_desc_depth()
343 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
345 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
346 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); in hix5hd2_set_desc_depth()
347 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
352 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
353 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); in hix5hd2_set_rx_fq()
354 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
359 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
360 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); in hix5hd2_set_rx_bq()
361 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
366 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
367 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); in hix5hd2_set_tx_bq()
368 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
373 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
374 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); in hix5hd2_set_tx_rq()
375 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
380 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr); in hix5hd2_set_desc_addr()
381 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr); in hix5hd2_set_desc_addr()
382 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr); in hix5hd2_set_desc_addr()
383 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr); in hix5hd2_set_desc_addr()
391 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_hw_init()
392 writel_relaxed(~0, priv->base + RAW_PMU_INT); in hix5hd2_hw_init()
394 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); in hix5hd2_hw_init()
395 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); in hix5hd2_hw_init()
396 writel_relaxed(0, priv->base + COL_SLOT_TIME); in hix5hd2_hw_init()
399 writel_relaxed(val, priv->base + IN_QUEUE_TH); in hix5hd2_hw_init()
401 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
402 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
410 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); in hix5hd2_irq_enable()
415 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_irq_disable()
420 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_enable()
421 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); in hix5hd2_port_enable()
426 writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); in hix5hd2_port_disable()
427 writel_relaxed(0, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_disable()
433 const unsigned char *mac = dev->dev_addr; in hix5hd2_hw_set_mac_addr() local
436 val = mac[1] | (mac[0] << 8); in hix5hd2_hw_set_mac_addr()
437 writel_relaxed(val, priv->base + STATION_ADDR_HIGH); in hix5hd2_hw_set_mac_addr()
439 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); in hix5hd2_hw_set_mac_addr()
440 writel_relaxed(val, priv->base + STATION_ADDR_LOW); in hix5hd2_hw_set_mac_addr()
457 struct phy_device *phy = dev->phydev; in hix5hd2_adjust_link()
459 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) { in hix5hd2_adjust_link()
460 hix5hd2_config_port(dev, phy->speed, phy->duplex); in hix5hd2_adjust_link()
474 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); in hix5hd2_rx_refill()
476 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); in hix5hd2_rx_refill()
480 if (priv->rx_skb[pos]) { in hix5hd2_rx_refill()
483 skb = netdev_alloc_skb_ip_align(priv->netdev, len); in hix5hd2_rx_refill()
488 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE); in hix5hd2_rx_refill()
489 if (dma_mapping_error(priv->dev, addr)) { in hix5hd2_rx_refill()
494 desc = priv->rx_fq.desc + pos; in hix5hd2_rx_refill()
495 desc->buff_addr = cpu_to_le32(addr); in hix5hd2_rx_refill()
496 priv->rx_skb[pos] = skb; in hix5hd2_rx_refill()
497 desc->cmd = cpu_to_le32(DESC_VLD_FREE | in hix5hd2_rx_refill()
498 (len - 1) << DESC_BUFF_LEN_OFF); in hix5hd2_rx_refill()
506 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); in hix5hd2_rx_refill()
518 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); in hix5hd2_rx()
520 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); in hix5hd2_rx()
528 skb = priv->rx_skb[pos]; in hix5hd2_rx()
533 priv->rx_skb[pos] = NULL; in hix5hd2_rx()
535 desc = priv->rx_bq.desc + pos; in hix5hd2_rx()
536 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) & in hix5hd2_rx()
538 addr = le32_to_cpu(desc->buff_addr); in hix5hd2_rx()
539 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE, in hix5hd2_rx()
543 if (skb->len > MAC_MAX_FRAME_SIZE) { in hix5hd2_rx()
544 netdev_err(dev, "rcv len err, len = %d\n", skb->len); in hix5hd2_rx()
545 dev->stats.rx_errors++; in hix5hd2_rx()
546 dev->stats.rx_length_errors++; in hix5hd2_rx()
551 skb->protocol = eth_type_trans(skb, dev); in hix5hd2_rx()
552 napi_gro_receive(&priv->napi, skb); in hix5hd2_rx()
553 dev->stats.rx_packets++; in hix5hd2_rx()
554 dev->stats.rx_bytes += len; in hix5hd2_rx()
560 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); in hix5hd2_rx()
575 desc = priv->tx_ring.desc + pos; in hix5hd2_clean_sg_desc()
577 addr = le32_to_cpu(desc->linear_addr); in hix5hd2_clean_sg_desc()
578 len = le32_to_cpu(desc->linear_len); in hix5hd2_clean_sg_desc()
579 dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE); in hix5hd2_clean_sg_desc()
581 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in hix5hd2_clean_sg_desc()
582 addr = le32_to_cpu(desc->frags[i].addr); in hix5hd2_clean_sg_desc()
583 len = le32_to_cpu(desc->frags[i].size); in hix5hd2_clean_sg_desc()
584 dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE); in hix5hd2_clean_sg_desc()
600 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); in hix5hd2_xmit_reclaim()
602 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); in hix5hd2_xmit_reclaim()
606 skb = priv->tx_skb[pos]; in hix5hd2_xmit_reclaim()
613 bytes_compl += skb->len; in hix5hd2_xmit_reclaim()
614 desc = priv->tx_rq.desc + pos; in hix5hd2_xmit_reclaim()
616 if (skb_shinfo(skb)->nr_frags) { in hix5hd2_xmit_reclaim()
619 addr = le32_to_cpu(desc->buff_addr); in hix5hd2_xmit_reclaim()
620 dma_unmap_single(priv->dev, addr, skb->len, in hix5hd2_xmit_reclaim()
624 priv->tx_skb[pos] = NULL; in hix5hd2_xmit_reclaim()
630 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); in hix5hd2_xmit_reclaim()
637 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) in hix5hd2_xmit_reclaim()
638 netif_wake_queue(priv->netdev); in hix5hd2_xmit_reclaim()
645 struct net_device *dev = priv->netdev; in hix5hd2_poll()
653 task -= num; in hix5hd2_poll()
657 ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_poll()
658 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_poll()
673 int ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
675 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
678 napi_schedule(&priv->napi); in hix5hd2_interrupt()
689 if (skb_shinfo(skb)->nr_frags) in hix5hd2_get_desc_cmd()
691 cmd |= skb_shinfo(skb)->nr_frags << DESC_FRAGS_NUM_OFF; in hix5hd2_get_desc_cmd()
694 ((skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF); in hix5hd2_get_desc_cmd()
697 cmd |= (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF; in hix5hd2_get_desc_cmd()
711 desc = priv->tx_ring.desc + pos; in hix5hd2_fill_sg_desc()
713 desc->total_len = cpu_to_le32(skb->len); in hix5hd2_fill_sg_desc()
714 addr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), in hix5hd2_fill_sg_desc()
716 if (unlikely(dma_mapping_error(priv->dev, addr))) in hix5hd2_fill_sg_desc()
717 return -EINVAL; in hix5hd2_fill_sg_desc()
718 desc->linear_addr = cpu_to_le32(addr); in hix5hd2_fill_sg_desc()
719 desc->linear_len = cpu_to_le32(skb_headlen(skb)); in hix5hd2_fill_sg_desc()
721 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in hix5hd2_fill_sg_desc()
722 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in hix5hd2_fill_sg_desc()
725 addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE); in hix5hd2_fill_sg_desc()
726 ret = dma_mapping_error(priv->dev, addr); in hix5hd2_fill_sg_desc()
728 return -EINVAL; in hix5hd2_fill_sg_desc()
729 desc->frags[i].addr = cpu_to_le32(addr); in hix5hd2_fill_sg_desc()
730 desc->frags[i].size = cpu_to_le32(len); in hix5hd2_fill_sg_desc()
746 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); in hix5hd2_net_xmit()
747 if (unlikely(priv->tx_skb[pos])) { in hix5hd2_net_xmit()
748 dev->stats.tx_dropped++; in hix5hd2_net_xmit()
749 dev->stats.tx_fifo_errors++; in hix5hd2_net_xmit()
754 desc = priv->tx_bq.desc + pos; in hix5hd2_net_xmit()
756 cmd = hix5hd2_get_desc_cmd(skb, priv->hw_cap); in hix5hd2_net_xmit()
757 desc->cmd = cpu_to_le32(cmd); in hix5hd2_net_xmit()
759 if (skb_shinfo(skb)->nr_frags) { in hix5hd2_net_xmit()
763 dev->stats.tx_dropped++; in hix5hd2_net_xmit()
766 addr = priv->tx_ring.phys_addr + pos * sizeof(struct sg_desc); in hix5hd2_net_xmit()
768 addr = dma_map_single(priv->dev, skb->data, skb->len, in hix5hd2_net_xmit()
770 if (unlikely(dma_mapping_error(priv->dev, addr))) { in hix5hd2_net_xmit()
772 dev->stats.tx_dropped++; in hix5hd2_net_xmit()
776 desc->buff_addr = cpu_to_le32(addr); in hix5hd2_net_xmit()
778 priv->tx_skb[pos] = skb; in hix5hd2_net_xmit()
784 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); in hix5hd2_net_xmit()
787 dev->stats.tx_packets++; in hix5hd2_net_xmit()
788 dev->stats.tx_bytes += skb->len; in hix5hd2_net_xmit()
789 netdev_sent_queue(dev, skb->len); in hix5hd2_net_xmit()
801 struct sk_buff *skb = priv->rx_skb[i]; in hix5hd2_free_dma_desc_rings()
805 desc = priv->rx_fq.desc + i; in hix5hd2_free_dma_desc_rings()
806 addr = le32_to_cpu(desc->buff_addr); in hix5hd2_free_dma_desc_rings()
807 dma_unmap_single(priv->dev, addr, in hix5hd2_free_dma_desc_rings()
810 priv->rx_skb[i] = NULL; in hix5hd2_free_dma_desc_rings()
814 struct sk_buff *skb = priv->tx_skb[i]; in hix5hd2_free_dma_desc_rings()
818 desc = priv->tx_rq.desc + i; in hix5hd2_free_dma_desc_rings()
819 addr = le32_to_cpu(desc->buff_addr); in hix5hd2_free_dma_desc_rings()
820 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); in hix5hd2_free_dma_desc_rings()
822 priv->tx_skb[i] = NULL; in hix5hd2_free_dma_desc_rings()
832 ret = clk_prepare_enable(priv->mac_core_clk); in hix5hd2_net_open()
834 netdev_err(dev, "failed to enable mac core clk %d\n", ret); in hix5hd2_net_open()
838 ret = clk_prepare_enable(priv->mac_ifc_clk); in hix5hd2_net_open()
840 clk_disable_unprepare(priv->mac_core_clk); in hix5hd2_net_open()
841 netdev_err(dev, "failed to enable mac ifc clk %d\n", ret); in hix5hd2_net_open()
845 phy = of_phy_connect(dev, priv->phy_node, in hix5hd2_net_open()
846 &hix5hd2_adjust_link, 0, priv->phy_mode); in hix5hd2_net_open()
848 clk_disable_unprepare(priv->mac_ifc_clk); in hix5hd2_net_open()
849 clk_disable_unprepare(priv->mac_core_clk); in hix5hd2_net_open()
850 return -ENODEV; in hix5hd2_net_open()
859 napi_enable(&priv->napi); in hix5hd2_net_open()
873 napi_disable(&priv->napi); in hix5hd2_net_close()
877 if (dev->phydev) { in hix5hd2_net_close()
878 phy_stop(dev->phydev); in hix5hd2_net_close()
879 phy_disconnect(dev->phydev); in hix5hd2_net_close()
882 clk_disable_unprepare(priv->mac_ifc_clk); in hix5hd2_net_close()
883 clk_disable_unprepare(priv->mac_core_clk); in hix5hd2_net_close()
893 hix5hd2_net_close(priv->netdev); in hix5hd2_tx_timeout_task()
894 hix5hd2_net_open(priv->netdev); in hix5hd2_tx_timeout_task()
901 schedule_work(&priv->tx_timeout_task); in hix5hd2_net_timeout()
920 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_wait_ready()
921 void __iomem *base = priv->base; in hix5hd2_mdio_wait_ready() local
924 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { in hix5hd2_mdio_wait_ready()
926 return -ETIMEDOUT; in hix5hd2_mdio_wait_ready()
935 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_read()
936 void __iomem *base = priv->base; in hix5hd2_mdio_read() local
943 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); in hix5hd2_mdio_read()
948 val = readl_relaxed(base + MDIO_RDATA_STATUS); in hix5hd2_mdio_read()
950 dev_err(bus->parent, "SMI bus read not valid\n"); in hix5hd2_mdio_read()
951 ret = -ENODEV; in hix5hd2_mdio_read()
955 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); in hix5hd2_mdio_read()
963 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_write()
964 void __iomem *base = priv->base; in hix5hd2_mdio_write() local
971 writel_relaxed(val, base + MDIO_SINGLE_DATA); in hix5hd2_mdio_write()
972 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); in hix5hd2_mdio_write()
983 if (priv->pool[i].desc) { in hix5hd2_destroy_hw_desc_queue()
984 dma_free_coherent(priv->dev, priv->pool[i].size, in hix5hd2_destroy_hw_desc_queue()
985 priv->pool[i].desc, in hix5hd2_destroy_hw_desc_queue()
986 priv->pool[i].phys_addr); in hix5hd2_destroy_hw_desc_queue()
987 priv->pool[i].desc = NULL; in hix5hd2_destroy_hw_desc_queue()
994 struct device *dev = priv->dev; in hix5hd2_init_hw_desc_queue()
999 priv->rx_fq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
1000 priv->rx_bq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
1001 priv->tx_bq.count = TX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
1002 priv->tx_rq.count = TX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
1005 size = priv->pool[i].count * sizeof(struct hix5hd2_desc); in hix5hd2_init_hw_desc_queue()
1011 priv->pool[i].size = size; in hix5hd2_init_hw_desc_queue()
1012 priv->pool[i].desc = virt_addr; in hix5hd2_init_hw_desc_queue()
1013 priv->pool[i].phys_addr = phys_addr; in hix5hd2_init_hw_desc_queue()
1020 return -ENOMEM; in hix5hd2_init_hw_desc_queue()
1028 desc = dma_alloc_coherent(priv->dev, in hix5hd2_init_sg_desc_queue()
1032 return -ENOMEM; in hix5hd2_init_sg_desc_queue()
1034 priv->tx_ring.desc = desc; in hix5hd2_init_sg_desc_queue()
1035 priv->tx_ring.phys_addr = phys_addr; in hix5hd2_init_sg_desc_queue()
1042 if (priv->tx_ring.desc) { in hix5hd2_destroy_sg_desc_queue()
1043 dma_free_coherent(priv->dev, in hix5hd2_destroy_sg_desc_queue()
1045 priv->tx_ring.desc, priv->tx_ring.phys_addr); in hix5hd2_destroy_sg_desc_queue()
1046 priv->tx_ring.desc = NULL; in hix5hd2_destroy_sg_desc_queue()
1052 if (!priv->mac_core_rst) in hix5hd2_mac_core_reset()
1055 reset_control_assert(priv->mac_core_rst); in hix5hd2_mac_core_reset()
1056 reset_control_deassert(priv->mac_core_rst); in hix5hd2_mac_core_reset()
1079 reset_control_deassert(priv->phy_rst); in hix5hd2_phy_reset()
1080 hix5hd2_sleep_us(priv->phy_reset_delays[PRE_DELAY]); in hix5hd2_phy_reset()
1082 reset_control_assert(priv->phy_rst); in hix5hd2_phy_reset()
1086 hix5hd2_sleep_us(priv->phy_reset_delays[PULSE]); in hix5hd2_phy_reset()
1087 reset_control_deassert(priv->phy_rst); in hix5hd2_phy_reset()
1089 hix5hd2_sleep_us(priv->phy_reset_delays[POST_DELAY]); in hix5hd2_phy_reset()
1096 struct device *dev = &pdev->dev; in hix5hd2_dev_probe()
1097 struct device_node *node = dev->of_node; in hix5hd2_dev_probe()
1105 return -ENOMEM; in hix5hd2_dev_probe()
1110 priv->dev = dev; in hix5hd2_dev_probe()
1111 priv->netdev = ndev; in hix5hd2_dev_probe()
1113 priv->hw_cap = (unsigned long)device_get_match_data(dev); in hix5hd2_dev_probe()
1115 priv->base = devm_platform_ioremap_resource(pdev, 0); in hix5hd2_dev_probe()
1116 if (IS_ERR(priv->base)) { in hix5hd2_dev_probe()
1117 ret = PTR_ERR(priv->base); in hix5hd2_dev_probe()
1121 priv->ctrl_base = devm_platform_ioremap_resource(pdev, 1); in hix5hd2_dev_probe()
1122 if (IS_ERR(priv->ctrl_base)) { in hix5hd2_dev_probe()
1123 ret = PTR_ERR(priv->ctrl_base); in hix5hd2_dev_probe()
1127 priv->mac_core_clk = devm_clk_get(&pdev->dev, "mac_core"); in hix5hd2_dev_probe()
1128 if (IS_ERR(priv->mac_core_clk)) { in hix5hd2_dev_probe()
1129 netdev_err(ndev, "failed to get mac core clk\n"); in hix5hd2_dev_probe()
1130 ret = -ENODEV; in hix5hd2_dev_probe()
1134 ret = clk_prepare_enable(priv->mac_core_clk); in hix5hd2_dev_probe()
1136 netdev_err(ndev, "failed to enable mac core clk %d\n", ret); in hix5hd2_dev_probe()
1140 priv->mac_ifc_clk = devm_clk_get(&pdev->dev, "mac_ifc"); in hix5hd2_dev_probe()
1141 if (IS_ERR(priv->mac_ifc_clk)) in hix5hd2_dev_probe()
1142 priv->mac_ifc_clk = NULL; in hix5hd2_dev_probe()
1144 ret = clk_prepare_enable(priv->mac_ifc_clk); in hix5hd2_dev_probe()
1146 netdev_err(ndev, "failed to enable mac ifc clk %d\n", ret); in hix5hd2_dev_probe()
1150 priv->mac_core_rst = devm_reset_control_get(dev, "mac_core"); in hix5hd2_dev_probe()
1151 if (IS_ERR(priv->mac_core_rst)) in hix5hd2_dev_probe()
1152 priv->mac_core_rst = NULL; in hix5hd2_dev_probe()
1155 priv->mac_ifc_rst = devm_reset_control_get(dev, "mac_ifc"); in hix5hd2_dev_probe()
1156 if (IS_ERR(priv->mac_ifc_rst)) in hix5hd2_dev_probe()
1157 priv->mac_ifc_rst = NULL; in hix5hd2_dev_probe()
1159 priv->phy_rst = devm_reset_control_get(dev, "phy"); in hix5hd2_dev_probe()
1160 if (IS_ERR(priv->phy_rst)) { in hix5hd2_dev_probe()
1161 priv->phy_rst = NULL; in hix5hd2_dev_probe()
1165 priv->phy_reset_delays, in hix5hd2_dev_probe()
1174 ret = -ENOMEM; in hix5hd2_dev_probe()
1178 bus->priv = priv; in hix5hd2_dev_probe()
1179 bus->name = "hix5hd2_mii_bus"; in hix5hd2_dev_probe()
1180 bus->read = hix5hd2_mdio_read; in hix5hd2_dev_probe()
1181 bus->write = hix5hd2_mdio_write; in hix5hd2_dev_probe()
1182 bus->parent = &pdev->dev; in hix5hd2_dev_probe()
1183 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); in hix5hd2_dev_probe()
1184 priv->bus = bus; in hix5hd2_dev_probe()
1190 ret = of_get_phy_mode(node, &priv->phy_mode); in hix5hd2_dev_probe()
1192 netdev_err(ndev, "not find phy-mode\n"); in hix5hd2_dev_probe()
1196 priv->phy_node = of_parse_phandle(node, "phy-handle", 0); in hix5hd2_dev_probe()
1197 if (!priv->phy_node) { in hix5hd2_dev_probe()
1198 netdev_err(ndev, "not find phy-handle\n"); in hix5hd2_dev_probe()
1199 ret = -EINVAL; in hix5hd2_dev_probe()
1203 ndev->irq = platform_get_irq(pdev, 0); in hix5hd2_dev_probe()
1204 if (ndev->irq < 0) { in hix5hd2_dev_probe()
1205 ret = ndev->irq; in hix5hd2_dev_probe()
1209 ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt, in hix5hd2_dev_probe()
1210 0, pdev->name, ndev); in hix5hd2_dev_probe()
1219 netdev_warn(ndev, "using random MAC address %pM\n", in hix5hd2_dev_probe()
1220 ndev->dev_addr); in hix5hd2_dev_probe()
1223 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task); in hix5hd2_dev_probe()
1224 ndev->watchdog_timeo = 6 * HZ; in hix5hd2_dev_probe()
1225 ndev->priv_flags |= IFF_UNICAST_FLT; in hix5hd2_dev_probe()
1226 ndev->netdev_ops = &hix5hd2_netdev_ops; in hix5hd2_dev_probe()
1227 ndev->ethtool_ops = &hix5hd2_ethtools_ops; in hix5hd2_dev_probe()
1230 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_probe()
1231 ndev->hw_features |= NETIF_F_SG; in hix5hd2_dev_probe()
1233 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; in hix5hd2_dev_probe()
1234 ndev->vlan_features |= ndev->features; in hix5hd2_dev_probe()
1240 netif_napi_add(ndev, &priv->napi, hix5hd2_poll); in hix5hd2_dev_probe()
1242 if (HAS_CAP_TSO(priv->hw_cap)) { in hix5hd2_dev_probe()
1248 ret = register_netdev(priv->netdev); in hix5hd2_dev_probe()
1254 clk_disable_unprepare(priv->mac_ifc_clk); in hix5hd2_dev_probe()
1255 clk_disable_unprepare(priv->mac_core_clk); in hix5hd2_dev_probe()
1260 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_probe()
1262 netif_napi_del(&priv->napi); in hix5hd2_dev_probe()
1265 of_node_put(priv->phy_node); in hix5hd2_dev_probe()
1271 clk_disable_unprepare(priv->mac_ifc_clk); in hix5hd2_dev_probe()
1273 clk_disable_unprepare(priv->mac_core_clk); in hix5hd2_dev_probe()
1285 netif_napi_del(&priv->napi); in hix5hd2_dev_remove()
1287 mdiobus_unregister(priv->bus); in hix5hd2_dev_remove()
1288 mdiobus_free(priv->bus); in hix5hd2_dev_remove()
1290 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_remove()
1293 of_node_put(priv->phy_node); in hix5hd2_dev_remove()
1294 cancel_work_sync(&priv->tx_timeout_task); in hix5hd2_dev_remove()
1299 { .compatible = "hisilicon,hisi-gmac-v1", .data = (void *)GEMAC_V1 },
1300 { .compatible = "hisilicon,hisi-gmac-v2", .data = (void *)GEMAC_V2 },
1301 { .compatible = "hisilicon,hix5hd2-gmac", .data = (void *)GEMAC_V1 },
1302 { .compatible = "hisilicon,hi3798cv200-gmac", .data = (void *)GEMAC_V2 },
1303 { .compatible = "hisilicon,hi3516a-gmac", .data = (void *)GEMAC_V2 },
1311 .name = "hisi-gmac",
1320 MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver");
1322 MODULE_ALIAS("platform:hisi-gmac");