Lines Matching +full:queue +full:- +full:pkt +full:- +full:tx
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
20 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
26 struct gve_tx_ring *tx = &priv->tx[tx_qid]; in gve_xdp_tx_flush() local
28 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_tx_flush()
32 * We copy skb payloads into the registered segment before writing Tx
33 * descriptors and ringing the Tx doorbell.
35 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
41 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
43 if (unlikely(!fifo->base)) { in gve_tx_fifo_init()
44 netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n", in gve_tx_fifo_init()
45 fifo->qpl->id); in gve_tx_fifo_init()
46 return -ENOMEM; in gve_tx_fifo_init()
49 fifo->size = fifo->qpl->num_entries * PAGE_SIZE; in gve_tx_fifo_init()
50 atomic_set(&fifo->available, fifo->size); in gve_tx_fifo_init()
51 fifo->head = 0; in gve_tx_fifo_init()
57 WARN(atomic_read(&fifo->available) != fifo->size, in gve_tx_fifo_release()
58 "Releasing non-empty fifo"); in gve_tx_fifo_release()
60 vunmap(fifo->base); in gve_tx_fifo_release()
66 return (fifo->head + bytes < fifo->size) ? 0 : fifo->size - fifo->head; in gve_tx_fifo_pad_alloc_one_frag()
71 return (atomic_read(&fifo->available) <= bytes) ? false : true; in gve_tx_fifo_can_alloc()
74 /* gve_tx_alloc_fifo - Allocate fragment(s) from Tx FIFO
77 * @iov: Scatter-gather elements to fill with allocation fragment base/len
105 iov[0].iov_offset = fifo->head; in gve_tx_alloc_fifo()
107 fifo->head += bytes; in gve_tx_alloc_fifo()
109 if (fifo->head > fifo->size) { in gve_tx_alloc_fifo()
114 overflow = fifo->head - fifo->size; in gve_tx_alloc_fifo()
115 iov[0].iov_len -= overflow; in gve_tx_alloc_fifo()
119 fifo->head = overflow; in gve_tx_alloc_fifo()
122 /* Re-align to a cacheline boundary */ in gve_tx_alloc_fifo()
123 aligned_head = L1_CACHE_ALIGN(fifo->head); in gve_tx_alloc_fifo()
124 padding = aligned_head - fifo->head; in gve_tx_alloc_fifo()
125 iov[nfrags - 1].iov_padding = padding; in gve_tx_alloc_fifo()
126 atomic_sub(bytes + padding, &fifo->available); in gve_tx_alloc_fifo()
127 fifo->head = aligned_head; in gve_tx_alloc_fifo()
129 if (fifo->head == fifo->size) in gve_tx_alloc_fifo()
130 fifo->head = 0; in gve_tx_alloc_fifo()
135 /* gve_tx_free_fifo - Return space to Tx FIFO
141 atomic_add(bytes, &fifo->available); in gve_tx_free_fifo()
149 for (i = 0; i < ARRAY_SIZE(info->iov); i++) { in gve_tx_clear_buffer_state()
150 space_freed += info->iov[i].iov_len + info->iov[i].iov_padding; in gve_tx_clear_buffer_state()
151 info->iov[i].iov_len = 0; in gve_tx_clear_buffer_state()
152 info->iov[i].iov_padding = 0; in gve_tx_clear_buffer_state()
157 static int gve_clean_xdp_done(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_clean_xdp_done() argument
168 idx = tx->done & tx->mask; in gve_clean_xdp_done()
169 info = &tx->info[idx]; in gve_clean_xdp_done()
170 tx->done++; in gve_clean_xdp_done()
172 if (unlikely(!info->xdp.size)) in gve_clean_xdp_done()
175 bytes += info->xdp.size; in gve_clean_xdp_done()
177 xsk_complete += info->xdp.is_xsk; in gve_clean_xdp_done()
179 info->xdp.size = 0; in gve_clean_xdp_done()
180 if (info->xdp_frame) { in gve_clean_xdp_done()
181 xdp_return_frame(info->xdp_frame); in gve_clean_xdp_done()
182 info->xdp_frame = NULL; in gve_clean_xdp_done()
187 gve_tx_free_fifo(&tx->tx_fifo, space_freed); in gve_clean_xdp_done()
188 if (xsk_complete > 0 && tx->xsk_pool) in gve_clean_xdp_done()
189 xsk_tx_completed(tx->xsk_pool, xsk_complete); in gve_clean_xdp_done()
190 u64_stats_update_begin(&tx->statss); in gve_clean_xdp_done()
191 tx->bytes_done += bytes; in gve_clean_xdp_done()
192 tx->pkt_done += pkts; in gve_clean_xdp_done()
193 u64_stats_update_end(&tx->statss); in gve_clean_xdp_done()
197 static int gve_clean_tx_done(struct gve_priv *priv, struct gve_tx_ring *tx,
203 struct gve_tx_ring *tx = &priv->tx[idx]; in gve_tx_stop_ring_gqi() local
209 gve_clean_tx_done(priv, tx, priv->tx_desc_cnt, false); in gve_tx_stop_ring_gqi()
210 netdev_tx_reset_queue(tx->netdev_txq); in gve_tx_stop_ring_gqi()
214 static void gve_tx_free_ring_gqi(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_tx_free_ring_gqi() argument
217 struct device *hdev = &priv->pdev->dev; in gve_tx_free_ring_gqi()
218 int idx = tx->q_num; in gve_tx_free_ring_gqi()
223 slots = tx->mask + 1; in gve_tx_free_ring_gqi()
224 dma_free_coherent(hdev, sizeof(*tx->q_resources), in gve_tx_free_ring_gqi()
225 tx->q_resources, tx->q_resources_bus); in gve_tx_free_ring_gqi()
226 tx->q_resources = NULL; in gve_tx_free_ring_gqi()
228 if (tx->tx_fifo.qpl) { in gve_tx_free_ring_gqi()
229 if (tx->tx_fifo.base) in gve_tx_free_ring_gqi()
230 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_free_ring_gqi()
232 qpl_id = gve_tx_qpl_id(priv, tx->q_num); in gve_tx_free_ring_gqi()
233 gve_free_queue_page_list(priv, tx->tx_fifo.qpl, qpl_id); in gve_tx_free_ring_gqi()
234 tx->tx_fifo.qpl = NULL; in gve_tx_free_ring_gqi()
237 bytes = sizeof(*tx->desc) * slots; in gve_tx_free_ring_gqi()
238 dma_free_coherent(hdev, bytes, tx->desc, tx->bus); in gve_tx_free_ring_gqi()
239 tx->desc = NULL; in gve_tx_free_ring_gqi()
241 vfree(tx->info); in gve_tx_free_ring_gqi()
242 tx->info = NULL; in gve_tx_free_ring_gqi()
244 netif_dbg(priv, drv, priv->dev, "freed tx queue %d\n", idx); in gve_tx_free_ring_gqi()
250 struct gve_tx_ring *tx = &priv->tx[idx]; in gve_tx_start_ring_gqi() local
254 tx->netdev_txq = netdev_get_tx_queue(priv->dev, idx); in gve_tx_start_ring_gqi()
260 struct gve_tx_ring *tx, in gve_tx_alloc_ring_gqi() argument
263 struct device *hdev = &priv->pdev->dev; in gve_tx_alloc_ring_gqi()
269 memset(tx, 0, sizeof(*tx)); in gve_tx_alloc_ring_gqi()
270 spin_lock_init(&tx->clean_lock); in gve_tx_alloc_ring_gqi()
271 spin_lock_init(&tx->xdp_lock); in gve_tx_alloc_ring_gqi()
272 tx->q_num = idx; in gve_tx_alloc_ring_gqi()
274 tx->mask = cfg->ring_size - 1; in gve_tx_alloc_ring_gqi()
277 tx->info = vcalloc(cfg->ring_size, sizeof(*tx->info)); in gve_tx_alloc_ring_gqi()
278 if (!tx->info) in gve_tx_alloc_ring_gqi()
279 return -ENOMEM; in gve_tx_alloc_ring_gqi()
281 /* alloc tx queue */ in gve_tx_alloc_ring_gqi()
282 bytes = sizeof(*tx->desc) * cfg->ring_size; in gve_tx_alloc_ring_gqi()
283 tx->desc = dma_alloc_coherent(hdev, bytes, &tx->bus, GFP_KERNEL); in gve_tx_alloc_ring_gqi()
284 if (!tx->desc) in gve_tx_alloc_ring_gqi()
287 tx->raw_addressing = cfg->raw_addressing; in gve_tx_alloc_ring_gqi()
288 tx->dev = hdev; in gve_tx_alloc_ring_gqi()
289 if (!tx->raw_addressing) { in gve_tx_alloc_ring_gqi()
290 qpl_id = gve_tx_qpl_id(priv, tx->q_num); in gve_tx_alloc_ring_gqi()
291 qpl_page_cnt = priv->tx_pages_per_qpl; in gve_tx_alloc_ring_gqi()
293 tx->tx_fifo.qpl = gve_alloc_queue_page_list(priv, qpl_id, in gve_tx_alloc_ring_gqi()
295 if (!tx->tx_fifo.qpl) in gve_tx_alloc_ring_gqi()
298 /* map Tx FIFO */ in gve_tx_alloc_ring_gqi()
299 if (gve_tx_fifo_init(priv, &tx->tx_fifo)) in gve_tx_alloc_ring_gqi()
303 tx->q_resources = in gve_tx_alloc_ring_gqi()
305 sizeof(*tx->q_resources), in gve_tx_alloc_ring_gqi()
306 &tx->q_resources_bus, in gve_tx_alloc_ring_gqi()
308 if (!tx->q_resources) in gve_tx_alloc_ring_gqi()
314 if (!tx->raw_addressing) in gve_tx_alloc_ring_gqi()
315 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_alloc_ring_gqi()
317 if (!tx->raw_addressing) { in gve_tx_alloc_ring_gqi()
318 gve_free_queue_page_list(priv, tx->tx_fifo.qpl, qpl_id); in gve_tx_alloc_ring_gqi()
319 tx->tx_fifo.qpl = NULL; in gve_tx_alloc_ring_gqi()
322 dma_free_coherent(hdev, bytes, tx->desc, tx->bus); in gve_tx_alloc_ring_gqi()
323 tx->desc = NULL; in gve_tx_alloc_ring_gqi()
325 vfree(tx->info); in gve_tx_alloc_ring_gqi()
326 tx->info = NULL; in gve_tx_alloc_ring_gqi()
327 return -ENOMEM; in gve_tx_alloc_ring_gqi()
333 struct gve_tx_ring *tx = cfg->tx; in gve_tx_alloc_rings_gqi() local
337 if (cfg->start_idx + cfg->num_rings > cfg->qcfg->max_queues) { in gve_tx_alloc_rings_gqi()
338 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
339 "Cannot alloc more than the max num of Tx rings\n"); in gve_tx_alloc_rings_gqi()
340 return -EINVAL; in gve_tx_alloc_rings_gqi()
343 if (cfg->start_idx == 0) { in gve_tx_alloc_rings_gqi()
344 tx = kvcalloc(cfg->qcfg->max_queues, sizeof(struct gve_tx_ring), in gve_tx_alloc_rings_gqi()
346 if (!tx) in gve_tx_alloc_rings_gqi()
347 return -ENOMEM; in gve_tx_alloc_rings_gqi()
348 } else if (!tx) { in gve_tx_alloc_rings_gqi()
349 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
350 "Cannot alloc tx rings from a nonzero start idx without tx array\n"); in gve_tx_alloc_rings_gqi()
351 return -EINVAL; in gve_tx_alloc_rings_gqi()
354 for (i = cfg->start_idx; i < cfg->start_idx + cfg->num_rings; i++) { in gve_tx_alloc_rings_gqi()
355 err = gve_tx_alloc_ring_gqi(priv, cfg, &tx[i], i); in gve_tx_alloc_rings_gqi()
357 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
358 "Failed to alloc tx ring=%d: err=%d\n", in gve_tx_alloc_rings_gqi()
364 cfg->tx = tx; in gve_tx_alloc_rings_gqi()
369 gve_tx_free_ring_gqi(priv, &tx[j], cfg); in gve_tx_alloc_rings_gqi()
370 if (cfg->start_idx == 0) in gve_tx_alloc_rings_gqi()
371 kvfree(tx); in gve_tx_alloc_rings_gqi()
378 struct gve_tx_ring *tx = cfg->tx; in gve_tx_free_rings_gqi() local
381 if (!tx) in gve_tx_free_rings_gqi()
384 for (i = cfg->start_idx; i < cfg->start_idx + cfg->num_rings; i++) in gve_tx_free_rings_gqi()
385 gve_tx_free_ring_gqi(priv, &tx[i], cfg); in gve_tx_free_rings_gqi()
387 if (cfg->start_idx == 0) { in gve_tx_free_rings_gqi()
388 kvfree(tx); in gve_tx_free_rings_gqi()
389 cfg->tx = NULL; in gve_tx_free_rings_gqi()
393 /* gve_tx_avail - Calculates the number of slots available in the ring
394 * @tx: tx ring to check
398 * The capacity of the queue is mask + 1. We don't need to reserve an entry.
400 static inline u32 gve_tx_avail(struct gve_tx_ring *tx) in gve_tx_avail() argument
402 return tx->mask + 1 - (tx->req - tx->done); in gve_tx_avail()
405 static inline int gve_skb_fifo_bytes_required(struct gve_tx_ring *tx, in gve_skb_fifo_bytes_required() argument
413 min_t(int, GVE_GQ_TX_MIN_PKT_DESC_BYTES, skb->len); in gve_skb_fifo_bytes_required()
415 pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, in gve_skb_fifo_bytes_required()
418 align_hdr_pad = L1_CACHE_ALIGN(hlen) - hlen; in gve_skb_fifo_bytes_required()
419 bytes = align_hdr_pad + pad_bytes + skb->len; in gve_skb_fifo_bytes_required()
434 if (info->skb) { in gve_tx_unmap_buf()
450 static inline bool gve_can_tx(struct gve_tx_ring *tx, int bytes_required) in gve_can_tx() argument
454 if (!tx->raw_addressing) in gve_can_tx()
455 can_alloc = gve_tx_fifo_can_alloc(&tx->tx_fifo, bytes_required); in gve_can_tx()
457 return (gve_tx_avail(tx) >= MAX_TX_DESC_NEEDED && can_alloc); in gve_can_tx()
462 /* Stops the queue if the skb cannot be transmitted. */
463 static int gve_maybe_stop_tx(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_maybe_stop_tx() argument
471 if (!tx->raw_addressing) in gve_maybe_stop_tx()
472 bytes_required = gve_skb_fifo_bytes_required(tx, skb); in gve_maybe_stop_tx()
474 if (likely(gve_can_tx(tx, bytes_required))) in gve_maybe_stop_tx()
477 ret = -EBUSY; in gve_maybe_stop_tx()
478 spin_lock(&tx->clean_lock); in gve_maybe_stop_tx()
479 nic_done = gve_tx_load_event_counter(priv, tx); in gve_maybe_stop_tx()
480 to_do = nic_done - tx->done; in gve_maybe_stop_tx()
482 /* Only try to clean if there is hope for TX */ in gve_maybe_stop_tx()
483 if (to_do + gve_tx_avail(tx) >= MAX_TX_DESC_NEEDED) { in gve_maybe_stop_tx()
486 gve_clean_tx_done(priv, tx, to_do, false); in gve_maybe_stop_tx()
488 if (likely(gve_can_tx(tx, bytes_required))) in gve_maybe_stop_tx()
492 /* No space, so stop the queue */ in gve_maybe_stop_tx()
493 tx->stop_queue++; in gve_maybe_stop_tx()
494 netif_tx_stop_queue(tx->netdev_txq); in gve_maybe_stop_tx()
496 spin_unlock(&tx->clean_lock); in gve_maybe_stop_tx()
506 /* l4_hdr_offset and csum_offset are in units of 16-bit words */ in gve_tx_fill_pkt_desc()
508 pkt_desc->pkt.type_flags = GVE_TXD_TSO | GVE_TXF_L4CSUM; in gve_tx_fill_pkt_desc()
509 pkt_desc->pkt.l4_csum_offset = csum_offset >> 1; in gve_tx_fill_pkt_desc()
510 pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1; in gve_tx_fill_pkt_desc()
512 pkt_desc->pkt.type_flags = GVE_TXD_STD | GVE_TXF_L4CSUM; in gve_tx_fill_pkt_desc()
513 pkt_desc->pkt.l4_csum_offset = csum_offset >> 1; in gve_tx_fill_pkt_desc()
514 pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1; in gve_tx_fill_pkt_desc()
516 pkt_desc->pkt.type_flags = GVE_TXD_STD; in gve_tx_fill_pkt_desc()
517 pkt_desc->pkt.l4_csum_offset = 0; in gve_tx_fill_pkt_desc()
518 pkt_desc->pkt.l4_hdr_offset = 0; in gve_tx_fill_pkt_desc()
520 pkt_desc->pkt.desc_cnt = desc_cnt; in gve_tx_fill_pkt_desc()
521 pkt_desc->pkt.len = cpu_to_be16(pkt_len); in gve_tx_fill_pkt_desc()
522 pkt_desc->pkt.seg_len = cpu_to_be16(hlen); in gve_tx_fill_pkt_desc()
523 pkt_desc->pkt.seg_addr = cpu_to_be64(addr); in gve_tx_fill_pkt_desc()
529 BUILD_BUG_ON(sizeof(mtd_desc->mtd) != sizeof(mtd_desc->pkt)); in gve_tx_fill_mtd_desc()
531 mtd_desc->mtd.type_flags = GVE_TXD_MTD | GVE_MTD_SUBTYPE_PATH; in gve_tx_fill_mtd_desc()
532 mtd_desc->mtd.path_state = GVE_MTD_PATH_STATE_DEFAULT | in gve_tx_fill_mtd_desc()
534 mtd_desc->mtd.path_hash = cpu_to_be32(skb->hash); in gve_tx_fill_mtd_desc()
535 mtd_desc->mtd.reserved0 = 0; in gve_tx_fill_mtd_desc()
536 mtd_desc->mtd.reserved1 = 0; in gve_tx_fill_mtd_desc()
544 seg_desc->seg.type_flags = GVE_TXD_SEG; in gve_tx_fill_seg_desc()
547 seg_desc->seg.type_flags |= GVE_TXSF_IPV6; in gve_tx_fill_seg_desc()
548 seg_desc->seg.l3_offset = l3_offset >> 1; in gve_tx_fill_seg_desc()
549 seg_desc->seg.mss = cpu_to_be16(gso_size); in gve_tx_fill_seg_desc()
551 seg_desc->seg.seg_len = cpu_to_be16(len); in gve_tx_fill_seg_desc()
552 seg_desc->seg.seg_addr = cpu_to_be64(addr); in gve_tx_fill_seg_desc()
558 u64 last_page = (iov_offset + iov_len - 1) / PAGE_SIZE; in gve_dma_sync_for_device()
566 static int gve_tx_add_skb_copy(struct gve_priv *priv, struct gve_tx_ring *tx, struct sk_buff *skb) in gve_tx_add_skb_copy() argument
571 int mtd_desc_nr = !!skb->l4_hash; in gve_tx_add_skb_copy()
573 u32 idx = tx->req & tx->mask; in gve_tx_add_skb_copy()
579 info = &tx->info[idx]; in gve_tx_add_skb_copy()
580 pkt_desc = &tx->desc[idx]; in gve_tx_add_skb_copy()
587 min_t(int, GVE_GQ_TX_MIN_PKT_DESC_BYTES, skb->len); in gve_tx_add_skb_copy()
589 info->skb = skb; in gve_tx_add_skb_copy()
593 pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, hlen); in gve_tx_add_skb_copy()
594 hdr_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, hlen + pad_bytes, in gve_tx_add_skb_copy()
595 &info->iov[0]); in gve_tx_add_skb_copy()
597 payload_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, skb->len - hlen, in gve_tx_add_skb_copy()
598 &info->iov[payload_iov]); in gve_tx_add_skb_copy()
600 gve_tx_fill_pkt_desc(pkt_desc, skb->csum_offset, skb->ip_summed, in gve_tx_add_skb_copy()
603 info->iov[hdr_nfrags - 1].iov_offset, skb->len); in gve_tx_add_skb_copy()
606 tx->tx_fifo.base + info->iov[hdr_nfrags - 1].iov_offset, in gve_tx_add_skb_copy()
608 gve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses, in gve_tx_add_skb_copy()
609 info->iov[hdr_nfrags - 1].iov_offset, in gve_tx_add_skb_copy()
610 info->iov[hdr_nfrags - 1].iov_len); in gve_tx_add_skb_copy()
614 next_idx = (tx->req + 1) & tx->mask; in gve_tx_add_skb_copy()
615 gve_tx_fill_mtd_desc(&tx->desc[next_idx], skb); in gve_tx_add_skb_copy()
619 next_idx = (tx->req + 1 + mtd_desc_nr + i - payload_iov) & tx->mask; in gve_tx_add_skb_copy()
620 seg_desc = &tx->desc[next_idx]; in gve_tx_add_skb_copy()
623 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_copy()
625 info->iov[i].iov_len, in gve_tx_add_skb_copy()
626 info->iov[i].iov_offset); in gve_tx_add_skb_copy()
629 tx->tx_fifo.base + info->iov[i].iov_offset, in gve_tx_add_skb_copy()
630 info->iov[i].iov_len); in gve_tx_add_skb_copy()
631 gve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses, in gve_tx_add_skb_copy()
632 info->iov[i].iov_offset, in gve_tx_add_skb_copy()
633 info->iov[i].iov_len); in gve_tx_add_skb_copy()
634 copy_offset += info->iov[i].iov_len; in gve_tx_add_skb_copy()
640 static int gve_tx_add_skb_no_copy(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_tx_add_skb_no_copy() argument
647 int mtd_desc_nr = !!skb->l4_hash; in gve_tx_add_skb_no_copy()
649 u32 idx = tx->req & tx->mask; in gve_tx_add_skb_no_copy()
654 info = &tx->info[idx]; in gve_tx_add_skb_no_copy()
655 pkt_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
660 * of the skb (which will contain the checksum because skb->csum_start and in gve_tx_add_skb_no_copy()
661 * skb->csum_offset are given relative to skb->head) in the first segment. in gve_tx_add_skb_no_copy()
666 info->skb = skb; in gve_tx_add_skb_no_copy()
668 addr = dma_map_single(tx->dev, skb->data, len, DMA_TO_DEVICE); in gve_tx_add_skb_no_copy()
669 if (unlikely(dma_mapping_error(tx->dev, addr))) { in gve_tx_add_skb_no_copy()
670 tx->dma_mapping_error++; in gve_tx_add_skb_no_copy()
676 num_descriptors = 1 + shinfo->nr_frags; in gve_tx_add_skb_no_copy()
682 gve_tx_fill_pkt_desc(pkt_desc, skb->csum_offset, skb->ip_summed, in gve_tx_add_skb_no_copy()
684 num_descriptors, hlen, addr, skb->len); in gve_tx_add_skb_no_copy()
687 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
688 mtd_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
696 len -= hlen; in gve_tx_add_skb_no_copy()
698 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
699 seg_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
701 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_no_copy()
705 for (i = 0; i < shinfo->nr_frags; i++) { in gve_tx_add_skb_no_copy()
706 const skb_frag_t *frag = &shinfo->frags[i]; in gve_tx_add_skb_no_copy()
708 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
709 seg_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
711 addr = skb_frag_dma_map(tx->dev, frag, 0, len, DMA_TO_DEVICE); in gve_tx_add_skb_no_copy()
712 if (unlikely(dma_mapping_error(tx->dev, addr))) { in gve_tx_add_skb_no_copy()
713 tx->dma_mapping_error++; in gve_tx_add_skb_no_copy()
716 tx->info[idx].skb = NULL; in gve_tx_add_skb_no_copy()
717 dma_unmap_len_set(&tx->info[idx], len, len); in gve_tx_add_skb_no_copy()
718 dma_unmap_addr_set(&tx->info[idx], dma, addr); in gve_tx_add_skb_no_copy()
721 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_no_copy()
728 i += num_descriptors - shinfo->nr_frags; in gve_tx_add_skb_no_copy()
729 while (i--) { in gve_tx_add_skb_no_copy()
733 idx--; in gve_tx_add_skb_no_copy()
734 gve_tx_unmap_buf(tx->dev, &tx->info[idx & tx->mask]); in gve_tx_add_skb_no_copy()
737 tx->dropped_pkt++; in gve_tx_add_skb_no_copy()
744 struct gve_tx_ring *tx; in gve_tx() local
747 WARN(skb_get_queue_mapping(skb) >= priv->tx_cfg.num_queues, in gve_tx()
748 "skb queue index out of range"); in gve_tx()
749 tx = &priv->tx[skb_get_queue_mapping(skb)]; in gve_tx()
750 if (unlikely(gve_maybe_stop_tx(priv, tx, skb))) { in gve_tx()
751 /* We need to ring the txq doorbell -- we have stopped the Tx in gve_tx()
752 * queue for want of resources, but prior calls to gve_tx() in gve_tx()
756 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_tx()
759 if (tx->raw_addressing) in gve_tx()
760 nsegs = gve_tx_add_skb_no_copy(priv, tx, skb); in gve_tx()
762 nsegs = gve_tx_add_skb_copy(priv, tx, skb); in gve_tx()
766 netdev_tx_sent_queue(tx->netdev_txq, skb->len); in gve_tx()
768 tx->req += nsegs; in gve_tx()
773 if (!netif_xmit_stopped(tx->netdev_txq) && netdev_xmit_more()) in gve_tx()
779 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_tx()
783 static int gve_tx_fill_xdp(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_tx_fill_xdp() argument
788 u32 reqi = tx->req; in gve_tx_fill_xdp()
790 pad = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, len); in gve_tx_fill_xdp()
793 info = &tx->info[reqi & tx->mask]; in gve_tx_fill_xdp()
794 info->xdp_frame = frame_p; in gve_tx_fill_xdp()
795 info->xdp.size = len; in gve_tx_fill_xdp()
796 info->xdp.is_xsk = is_xsk; in gve_tx_fill_xdp()
798 nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, pad + len, in gve_tx_fill_xdp()
799 &info->iov[0]); in gve_tx_fill_xdp()
801 ndescs = nfrags - iovi; in gve_tx_fill_xdp()
806 gve_tx_fill_pkt_desc(&tx->desc[reqi & tx->mask], 0, in gve_tx_fill_xdp()
808 info->iov[iovi].iov_len, in gve_tx_fill_xdp()
809 info->iov[iovi].iov_offset, len); in gve_tx_fill_xdp()
811 gve_tx_fill_seg_desc(&tx->desc[reqi & tx->mask], in gve_tx_fill_xdp()
813 info->iov[iovi].iov_len, in gve_tx_fill_xdp()
814 info->iov[iovi].iov_offset); in gve_tx_fill_xdp()
816 memcpy(tx->tx_fifo.base + info->iov[iovi].iov_offset, in gve_tx_fill_xdp()
817 data + offset, info->iov[iovi].iov_len); in gve_tx_fill_xdp()
818 gve_dma_sync_for_device(&priv->pdev->dev, in gve_tx_fill_xdp()
819 tx->tx_fifo.qpl->page_buses, in gve_tx_fill_xdp()
820 info->iov[iovi].iov_offset, in gve_tx_fill_xdp()
821 info->iov[iovi].iov_len); in gve_tx_fill_xdp()
822 offset += info->iov[iovi].iov_len; in gve_tx_fill_xdp()
834 struct gve_tx_ring *tx; in gve_xdp_xmit() local
838 return -EINVAL; in gve_xdp_xmit()
841 smp_processor_id() % priv->num_xdp_queues); in gve_xdp_xmit()
843 tx = &priv->tx[qid]; in gve_xdp_xmit()
845 spin_lock(&tx->xdp_lock); in gve_xdp_xmit()
847 err = gve_xdp_xmit_one(priv, tx, frames[i]->data, in gve_xdp_xmit()
848 frames[i]->len, frames[i]); in gve_xdp_xmit()
854 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_xmit()
856 spin_unlock(&tx->xdp_lock); in gve_xdp_xmit()
858 u64_stats_update_begin(&tx->statss); in gve_xdp_xmit()
859 tx->xdp_xmit += n; in gve_xdp_xmit()
860 tx->xdp_xmit_errors += n - i; in gve_xdp_xmit()
861 u64_stats_update_end(&tx->statss); in gve_xdp_xmit()
866 int gve_xdp_xmit_one(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_xdp_xmit_one() argument
871 if (!gve_can_tx(tx, len + GVE_GQ_TX_MIN_PKT_DESC_BYTES - 1)) in gve_xdp_xmit_one()
872 return -EBUSY; in gve_xdp_xmit_one()
874 nsegs = gve_tx_fill_xdp(priv, tx, data, len, frame_p, false); in gve_xdp_xmit_one()
875 tx->req += nsegs; in gve_xdp_xmit_one()
882 static int gve_clean_tx_done(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_clean_tx_done() argument
893 idx = tx->done & tx->mask; in gve_clean_tx_done()
894 netif_info(priv, tx_done, priv->dev, in gve_clean_tx_done()
896 tx->q_num, __func__, idx, tx->req, tx->done); in gve_clean_tx_done()
897 info = &tx->info[idx]; in gve_clean_tx_done()
898 skb = info->skb; in gve_clean_tx_done()
901 if (tx->raw_addressing) in gve_clean_tx_done()
902 gve_tx_unmap_buf(tx->dev, info); in gve_clean_tx_done()
903 tx->done++; in gve_clean_tx_done()
906 info->skb = NULL; in gve_clean_tx_done()
907 bytes += skb->len; in gve_clean_tx_done()
910 if (tx->raw_addressing) in gve_clean_tx_done()
916 if (!tx->raw_addressing) in gve_clean_tx_done()
917 gve_tx_free_fifo(&tx->tx_fifo, space_freed); in gve_clean_tx_done()
918 u64_stats_update_begin(&tx->statss); in gve_clean_tx_done()
919 tx->bytes_done += bytes; in gve_clean_tx_done()
920 tx->pkt_done += pkts; in gve_clean_tx_done()
921 u64_stats_update_end(&tx->statss); in gve_clean_tx_done()
922 netdev_tx_completed_queue(tx->netdev_txq, pkts, bytes); in gve_clean_tx_done()
924 /* start the queue if we've stopped it */ in gve_clean_tx_done()
929 if (try_to_wake && netif_tx_queue_stopped(tx->netdev_txq) && in gve_clean_tx_done()
930 likely(gve_can_tx(tx, GVE_TX_START_THRESH))) { in gve_clean_tx_done()
931 tx->wake_queue++; in gve_clean_tx_done()
932 netif_tx_wake_queue(tx->netdev_txq); in gve_clean_tx_done()
939 struct gve_tx_ring *tx) in gve_tx_load_event_counter() argument
941 u32 counter_index = be32_to_cpu(tx->q_resources->counter_index); in gve_tx_load_event_counter()
942 __be32 counter = READ_ONCE(priv->counter_array[counter_index]); in gve_tx_load_event_counter()
947 static int gve_xsk_tx(struct gve_priv *priv, struct gve_tx_ring *tx, in gve_xsk_tx() argument
954 spin_lock(&tx->xdp_lock); in gve_xsk_tx()
956 if (!gve_can_tx(tx, GVE_TX_START_THRESH)) in gve_xsk_tx()
959 if (!xsk_tx_peek_desc(tx->xsk_pool, &desc)) { in gve_xsk_tx()
960 tx->xdp_xsk_done = tx->xdp_xsk_wakeup; in gve_xsk_tx()
964 data = xsk_buff_raw_get_data(tx->xsk_pool, desc.addr); in gve_xsk_tx()
965 nsegs = gve_tx_fill_xdp(priv, tx, data, desc.len, NULL, true); in gve_xsk_tx()
966 tx->req += nsegs; in gve_xsk_tx()
971 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xsk_tx()
972 xsk_tx_release(tx->xsk_pool); in gve_xsk_tx()
974 spin_unlock(&tx->xdp_lock); in gve_xsk_tx()
980 struct gve_priv *priv = block->priv; in gve_xdp_poll()
981 struct gve_tx_ring *tx = block->tx; in gve_xdp_poll() local
987 nic_done = gve_tx_load_event_counter(priv, tx); in gve_xdp_poll()
988 to_do = min_t(u32, (nic_done - tx->done), budget); in gve_xdp_poll()
989 gve_clean_xdp_done(priv, tx, to_do); in gve_xdp_poll()
990 repoll = nic_done != tx->done; in gve_xdp_poll()
992 if (tx->xsk_pool) { in gve_xdp_poll()
993 int sent = gve_xsk_tx(priv, tx, budget); in gve_xdp_poll()
995 u64_stats_update_begin(&tx->statss); in gve_xdp_poll()
996 tx->xdp_xsk_sent += sent; in gve_xdp_poll()
997 u64_stats_update_end(&tx->statss); in gve_xdp_poll()
999 if (xsk_uses_need_wakeup(tx->xsk_pool)) in gve_xdp_poll()
1000 xsk_set_tx_need_wakeup(tx->xsk_pool); in gve_xdp_poll()
1009 struct gve_priv *priv = block->priv; in gve_tx_poll()
1010 struct gve_tx_ring *tx = block->tx; in gve_tx_poll() local
1018 /* In TX path, it may try to clean completed pkts in order to xmit, in gve_tx_poll()
1022 spin_lock(&tx->clean_lock); in gve_tx_poll()
1024 nic_done = gve_tx_load_event_counter(priv, tx); in gve_tx_poll()
1025 to_do = min_t(u32, (nic_done - tx->done), budget); in gve_tx_poll()
1026 gve_clean_tx_done(priv, tx, to_do, true); in gve_tx_poll()
1027 spin_unlock(&tx->clean_lock); in gve_tx_poll()
1029 return nic_done != tx->done; in gve_tx_poll()
1032 bool gve_tx_clean_pending(struct gve_priv *priv, struct gve_tx_ring *tx) in gve_tx_clean_pending() argument
1034 u32 nic_done = gve_tx_load_event_counter(priv, tx); in gve_tx_clean_pending()
1036 return nic_done != tx->done; in gve_tx_clean_pending()