fungible/funeth/funeth_txrx.h

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
10 /* Tx descriptor size */
13 /* Size of device headers per Tx packet */
16 /* Number of gather list entries per Tx descriptor */
28 /* Max number of Tx descriptors for an sk_buff using a gather list. */
33 /* Max number of Tx descriptors for any packet. */
40 #define FUNETH_CQE_INFO_OFFSET (FUNETH_CQE_SIZE - sizeof(struct fun_cqe_info))
55 /* Per packet tailroom. Present only for 1-frag packets. */
66 	FUN_QSTATE_INIT_SW,   /* exists in SW, not on the device */
67 	FUN_QSTATE_INIT_FULL, /* exists both in SW and on device */
80 struct funeth_txq_stats {  /* per Tx queue SW counters */
81 	u64 tx_pkts;       /* # of Tx packets */
82 	u64 tx_bytes;      /* total bytes of Tx packets */
84 	u64 tx_tso;        /* # of non-encapsulated TSO super-packets */
85 	u64 tx_encap_tso;  /* # of encapsulated TSO super-packets */
86 	u64 tx_uso;        /* # of non-encapsulated UDP LSO super-packets */
92 	u64 tx_tls_pkts;   /* # of Tx TLS packets offloaded to HW */
93 	u64 tx_tls_bytes;  /* Tx bytes of HW-handled TLS payload */
94 	u64 tx_tls_fallback; /* attempted Tx TLS offloads punted to SW */
95 	u64 tx_tls_drops;  /* attempted Tx TLS offloads dropped */
98 struct funeth_tx_info {      /* per Tx descriptor state */
107 	u32 mask;               /* queue depth - 1 */
108 	u32 hw_qid;             /* device ID of the queue */
111 	struct device *dma_dev; /* device for DMA mappings */
112 	volatile __be64 *hw_wb; /* HW write-back location */
135 	u64 rx_bufs;       /* total # of Rx buffers provided to device */
152 	int node;              /* page node, or -1 if it is PF_MEMALLOC */
155 struct funeth_rx_cache {       /* cache of DMA-mapped previously used buffers */
159 	unsigned int mask;         /* depth - 1 */
166 	struct device *dma_dev;    /* device for DMA mappings */
171 	unsigned int cq_mask;      /* CQ depth - 1 */
180 	unsigned int rq_mask;      /* RQ depth - 1 */
194 	u32 hw_cqid;               /* device ID of the queue's CQ */
195 	u32 hw_sqid;               /* device ID of the queue's SQ */
203 		u64_stats_update_begin(&(q)->syncp); \
204 		(q)->stats.counter++; \
205 		u64_stats_update_end(&(q)->syncp); \
210 		seq = u64_stats_fetch_begin(&(q)->syncp); \
211 		stats_copy = (q)->stats; \
212 	} while (u64_stats_fetch_retry(&(q)->syncp, (seq)))
221 	u16 irq_idx;              /* index of MSI-X interrupt */
228 /* Return the start address of the idx-th Tx descriptor. */
232 	return q->desc + idx * FUNETH_SQE_SIZE;  in fun_tx_desc_addr()
237 	unsigned int tail = q->prod_cnt & q->mask;  in fun_txq_wr_db()
239 	writel(tail, q->db);  in fun_txq_wr_db()
244 	return cpu_to_mem(cpumask_first(&p->affinity_mask));  in fun_irq_node()