Lines Matching +full:inter +full:- +full:ic
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
238 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ argument
240 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) argument
281 /* weighted round-robin scheduling (WRRS) */
381 * to the 3-bit hash value generated */
581 __be16 phcs; /* Pseudo-header Checksum */
606 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
609 #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
614 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
615 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
616 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
617 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
618 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
619 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
620 u32 rbyt; /* 0x.69c - Receive Byte Counter */
621 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
622 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
623 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
624 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
625 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
626 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
627 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
628 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
629 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
630 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
631 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
632 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
633 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
634 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
635 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
636 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
637 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
638 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
639 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
640 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
641 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
642 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
643 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
644 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
645 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
646 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
647 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
648 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
650 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
651 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
652 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
653 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
654 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
655 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
656 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
657 u32 car1; /* 0x.730 - Carry Register One */
658 u32 car2; /* 0x.734 - Carry Register Two */
659 u32 cam1; /* 0x.738 - Carry Mask Register One */
660 u32 cam2; /* 0x.73c - Carry Mask Register Two */
688 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
696 u32 tsec_id; /* 0x.000 - Controller ID register */
697 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
699 u32 ievent; /* 0x.010 - Interrupt Event Register */
700 u32 imask; /* 0x.014 - Interrupt Mask Register */
701 u32 edis; /* 0x.018 - Error Disabled Register */
702 u32 emapg; /* 0x.01c - Group Error mapping register */
703 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
704 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
705 u32 ptv; /* 0x.028 - Pause Time Value Register */
706 u32 dmactrl; /* 0x.02c - DMA Control Register */
707 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
709 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
711 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
713 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
715 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
718 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
720 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
721 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
723 u32 tctrl; /* 0x.100 - Transmit Control Register */
724 u32 tstat; /* 0x.104 - Transmit Status Register */
725 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
726 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
727 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
728 u32 tqueue; /* 0x.114 - Transmit queue control register */
730 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
731 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
733 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
735 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
737 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
739 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
741 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
743 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
745 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
747 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
749 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
751 u32 tbaseh; /* 0x.200 - TxBD base address high */
752 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
754 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
756 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
758 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
760 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
762 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
764 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
766 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
768 u32 rctrl; /* 0x.300 - Receive Control Register */
769 u32 rstat; /* 0x.304 - Receive Status Register */
771 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
772 u32 rqueue; /* 0x.314 - Receive queue control register */
773 u32 rir0; /* 0x.318 - Ring mapping register 0 */
774 u32 rir1; /* 0x.31c - Ring mapping register 1 */
775 u32 rir2; /* 0x.320 - Ring mapping register 2 */
776 u32 rir3; /* 0x.324 - Ring mapping register 3 */
778 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
779 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
780 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
781 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
782 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
784 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
786 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
788 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
790 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
792 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
794 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
796 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
798 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
800 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
802 u32 rbaseh; /* 0x.400 - RxBD base address high */
803 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
805 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
807 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
809 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
811 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
813 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
815 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
817 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
819 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
820 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
821 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
822 u32 hafdup; /* 0x.50c - Half Duplex Register */
823 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
826 u32 ifctrl; /* 0x.538 - Interface control register */
827 u32 ifstat; /* 0x.53c - Interface Status Register */
828 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
829 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
830 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
831 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
832 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
833 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
834 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
835 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
836 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
837 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
838 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
839 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
840 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
841 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
842 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
843 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
844 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
845 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
846 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
847 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
848 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
849 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
850 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
851 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
852 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
853 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
854 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
855 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
856 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
857 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
858 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
859 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
861 struct rmon_mib rmon; /* 0x.680-0x.73c */
862 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
864 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
865 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
866 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
867 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
868 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
869 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
870 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
871 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
873 u32 gaddr0; /* 0x.880 - Group address register 0 */
874 u32 gaddr1; /* 0x.884 - Group address register 1 */
875 u32 gaddr2; /* 0x.888 - Group address register 2 */
876 u32 gaddr3; /* 0x.88c - Group address register 3 */
877 u32 gaddr4; /* 0x.890 - Group address register 4 */
878 u32 gaddr5; /* 0x.894 - Group address register 5 */
879 u32 gaddr6; /* 0x.898 - Group address register 6 */
880 u32 gaddr7; /* 0x.89c - Group address register 7 */
882 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
885 u32 attr; /* 0x.bf8 - Attributes Register */
886 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
887 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
888 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
889 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
890 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
891 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
892 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
893 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
894 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
896 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
898 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
900 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
902 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
904 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
906 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
908 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
910 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
913 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
914 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
915 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
916 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
918 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
919 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
920 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
921 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
922 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
923 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
924 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
925 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
927 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
928 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
929 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
930 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
931 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
932 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
933 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
934 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
981 * struct gfar_priv_tx_q - per tx queue structure
1038 * struct gfar_priv_rx_q - per rx queue structure
1046 * @rxcoalescing: enable/disable rx-coalescing
1082 * struct gfar_priv_grp - per group structure
1109 ((grp)->irqinfo[GFAR_##ID])
1207 /* wake-on-lan settings */
1220 return priv->errata & err; in gfar_has_errata()
1238 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_write_filer()
1240 gfar_write(®s->rqfar, far); in gfar_write_filer()
1241 gfar_write(®s->rqfcr, fcr); in gfar_write_filer()
1242 gfar_write(®s->rqfpr, fpr); in gfar_write_filer()
1248 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_read_filer()
1250 gfar_write(®s->rqfar, far); in gfar_read_filer()
1251 *fcr = gfar_read(®s->rqfcr); in gfar_read_filer()
1252 *fpr = gfar_read(®s->rqfpr); in gfar_read_filer()
1257 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_write_isrg()
1258 u32 __iomem *baddr = ®s->isrg0; in gfar_write_isrg()
1262 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { in gfar_write_isrg()
1263 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; in gfar_write_isrg()
1265 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { in gfar_write_isrg()
1269 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { in gfar_write_isrg()
1282 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_is_dma_stopped()
1284 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == in gfar_is_dma_stopped()
1290 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_is_rx_dma_stopped()
1292 return gfar_read(®s->ievent) & IEVENT_GRSC; in gfar_is_rx_dma_stopped()
1298 /* The powerpc-specific eieio() is used, as wmb() has too strong in gfar_wmb()
1302 * some point, the set of architecture-independent barrier functions in gfar_wmb()
1313 u32 lstatus = be32_to_cpu(bdp->lstatus); in gfar_clear_txbd_status()
1316 bdp->lstatus = cpu_to_be32(lstatus); in gfar_clear_txbd_status()
1321 if (rxq->next_to_clean > rxq->next_to_use) in gfar_rxbd_unused()
1322 return rxq->next_to_clean - rxq->next_to_use - 1; in gfar_rxbd_unused()
1324 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1; in gfar_rxbd_unused()
1333 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1; in gfar_rxbd_dma_lastfree()
1334 bdp = &rxq->rx_bd_base[i]; in gfar_rxbd_dma_lastfree()
1335 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base); in gfar_rxbd_dma_lastfree()
1336 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base; in gfar_rxbd_dma_lastfree()