Lines Matching defs:tgec_regs
68 struct tgec_regs { struct
69 u32 tgec_id; /* 0x000 Controller ID */
70 u32 reserved001[1]; /* 0x004 */
71 u32 command_config; /* 0x008 Control and configuration */
72 u32 mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
73 u32 mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
74 u32 maxfrm; /* 0x014 Maximum frame length */
75 u32 pause_quant; /* 0x018 Pause quanta */
76 u32 rx_fifo_sections; /* 0x01c */
77 u32 tx_fifo_sections; /* 0x020 */
78 u32 rx_fifo_almost_f_e; /* 0x024 */
79 u32 tx_fifo_almost_f_e; /* 0x028 */
80 u32 hashtable_ctrl; /* 0x02c Hash table control */
81 u32 mdio_cfg_status; /* 0x030 */
82 u32 mdio_command; /* 0x034 */
83 u32 mdio_data; /* 0x038 */
84 u32 mdio_regaddr; /* 0x03c */
85 u32 status; /* 0x040 */
86 u32 tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
87 u32 mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
88 u32 mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
89 u32 rx_fifo_ptr_rd; /* 0x050 */
90 u32 rx_fifo_ptr_wr; /* 0x054 */
91 u32 tx_fifo_ptr_rd; /* 0x058 */
92 u32 tx_fifo_ptr_wr; /* 0x05c */
93 u32 imask; /* 0x060 Interrupt mask */
94 u32 ievent; /* 0x064 Interrupt event */
95 u32 udp_port; /* 0x068 Defines a UDP Port number */
96 u32 type_1588v2; /* 0x06c Type field for 1588v2 */
97 u32 reserved070[4]; /* 0x070 */
99 u32 tfrm_u; /* 80 aFramesTransmittedOK */
100 u32 tfrm_l; /* 84 aFramesTransmittedOK */
101 u32 rfrm_u; /* 88 aFramesReceivedOK */
102 u32 rfrm_l; /* 8c aFramesReceivedOK */
103 u32 rfcs_u; /* 90 aFrameCheckSequenceErrors */
104 u32 rfcs_l; /* 94 aFrameCheckSequenceErrors */
105 u32 raln_u; /* 98 aAlignmentErrors */
106 u32 raln_l; /* 9c aAlignmentErrors */
107 u32 txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */
108 u32 txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */
109 u32 rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */
110 u32 rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */
111 u32 rlong_u; /* B0 aFrameTooLongErrors */
112 u32 rlong_l; /* B4 aFrameTooLongErrors */
113 u32 rflr_u; /* B8 aInRangeLengthErrors */
114 u32 rflr_l; /* Bc aInRangeLengthErrors */
115 u32 tvlan_u; /* C0 VLANTransmittedOK */
116 u32 tvlan_l; /* C4 VLANTransmittedOK */
117 u32 rvlan_u; /* C8 VLANReceivedOK */
118 u32 rvlan_l; /* Cc VLANReceivedOK */
119 u32 toct_u; /* D0 if_out_octets */
120 u32 toct_l; /* D4 if_out_octets */
121 u32 roct_u; /* D8 if_in_octets */
122 u32 roct_l; /* Dc if_in_octets */
123 u32 ruca_u; /* E0 if_in_ucast_pkts */
124 u32 ruca_l; /* E4 if_in_ucast_pkts */
125 u32 rmca_u; /* E8 ifInMulticastPkts */
126 u32 rmca_l; /* Ec ifInMulticastPkts */
127 u32 rbca_u; /* F0 ifInBroadcastPkts */
128 u32 rbca_l; /* F4 ifInBroadcastPkts */
129 u32 terr_u; /* F8 if_out_errors */
130 u32 terr_l; /* Fc if_out_errors */
131 u32 reserved100[2]; /* 100-108 */
132 u32 tuca_u; /* 108 if_out_ucast_pkts */
133 u32 tuca_l; /* 10c if_out_ucast_pkts */
134 u32 tmca_u; /* 110 ifOutMulticastPkts */
135 u32 tmca_l; /* 114 ifOutMulticastPkts */
136 u32 tbca_u; /* 118 ifOutBroadcastPkts */
137 u32 tbca_l; /* 11c ifOutBroadcastPkts */
138 u32 rdrp_u; /* 120 etherStatsDropEvents */
139 u32 rdrp_l; /* 124 etherStatsDropEvents */
140 u32 reoct_u; /* 128 etherStatsOctets */
141 u32 reoct_l; /* 12c etherStatsOctets */
142 u32 rpkt_u; /* 130 etherStatsPkts */
143 u32 rpkt_l; /* 134 etherStatsPkts */
144 u32 trund_u; /* 138 etherStatsUndersizePkts */
145 u32 trund_l; /* 13c etherStatsUndersizePkts */
146 u32 r64_u; /* 140 etherStatsPkts64Octets */
147 u32 r64_l; /* 144 etherStatsPkts64Octets */
148 u32 r127_u; /* 148 etherStatsPkts65to127Octets */
149 u32 r127_l; /* 14c etherStatsPkts65to127Octets */
150 u32 r255_u; /* 150 etherStatsPkts128to255Octets */
151 u32 r255_l; /* 154 etherStatsPkts128to255Octets */
152 u32 r511_u; /* 158 etherStatsPkts256to511Octets */
153 u32 r511_l; /* 15c etherStatsPkts256to511Octets */
154 u32 r1023_u; /* 160 etherStatsPkts512to1023Octets */
155 u32 r1023_l; /* 164 etherStatsPkts512to1023Octets */
156 u32 r1518_u; /* 168 etherStatsPkts1024to1518Octets */
180 struct tgec_regs __iomem *regs; argument