Lines Matching +full:rx +full:- +full:pcs
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
29 #define TBICON_AN_SENSE 0x0100 /* Auto-negotiation sense enable */
165 u32 tmr_ctrl; /* 0x020 Time-stamp Control register */
166 u32 tmr_pevent; /* 0x024 Time-stamp event register */
173 u32 igaddr[8]; /* 0x080-0x09C Individual/group address */
174 u32 gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
179 u32 hafdup; /* 0x10C Half-duplex */
186 u32 exact_match1; /* octets 1-4 */
187 u32 exact_match2; /* octets 5-6 */
188 } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */
190 u32 tr64; /* 0x200 Tx and Rx 64 byte frame counter */
191 u32 tr127; /* 0x204 Tx and Rx 65 to 127 byte frame counter */
192 u32 tr255; /* 0x208 Tx and Rx 128 to 255 byte frame counter */
193 u32 tr511; /* 0x20C Tx and Rx 256 to 511 byte frame counter */
194 u32 tr1k; /* 0x210 Tx and Rx 512 to 1023 byte frame counter */
195 u32 trmax; /* 0x214 Tx and Rx 1024 to 1518 byte frame counter */
197 /* 0x218 Tx and Rx 1519 to 1522 byte good VLAN frame count */
201 u32 rmca; /* 0x228 RMCA Rx multicast packet counter */
202 u32 rbca; /* 0x22C Rx broadcast packet counter */
203 u32 rxcf; /* 0x230 Rx control frame packet counter */
204 u32 rxpf; /* 0x234 Rx pause frame packet counter */
205 u32 rxuo; /* 0x238 Rx unknown OP code counter */
206 u32 raln; /* 0x23C Rx alignment error counter */
207 u32 rflr; /* 0x240 Rx frame length error counter */
208 u32 rcde; /* 0x244 Rx code error counter */
209 u32 rcse; /* 0x248 Rx carrier sense error counter */
210 u32 rund; /* 0x24C Rx undersize packet counter */
211 u32 rovr; /* 0x250 Rx oversize packet counter */
212 u32 rfrg; /* 0x254 Rx fragments counter */
213 u32 rjbr; /* 0x258 Rx jabber counter */
214 u32 rdrp; /* 0x25C Rx drop */
242 /* struct dtsec_cfg - dTSEC configuration
243 * Transmit half-duplex flow control, under software control for 10/100-Mbps
244 * half-duplex media. If set, back pressure is applied to media by raising
253 * standard 512-bit slot time window. If collisions are detected after this
265 * start-of-frame delimiter byte. The default value of 0x7 should be used in
268 * Packet alignment padding length. The specified number of bytes (1-31)
321 struct phylink_pcs pcs; member
326 cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT; in set_dflts()
327 cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW; in set_dflts()
328 cfg->tx_pad_crc = true; in set_dflts()
329 cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME; in set_dflts()
331 cfg->rx_prepend = DEFAULT_RX_PREPEND; in set_dflts()
332 cfg->ptp_tsu_en = true; in set_dflts()
333 cfg->ptp_exception_en = true; in set_dflts()
334 cfg->preamble_len = DEFAULT_PREAMBLE_LEN; in set_dflts()
335 cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD; in set_dflts()
336 cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1; in set_dflts()
337 cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2; in set_dflts()
338 cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT; in set_dflts()
339 cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG; in set_dflts()
340 cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME; in set_dflts()
349 iowrite32be(tmp, ®s->macstnaddr1); in set_mac_address()
352 iowrite32be(tmp, ®s->macstnaddr2); in set_mac_address()
364 iowrite32be(MACCFG1_SOFT_RESET, ®s->maccfg1); in init()
365 iowrite32be(0, ®s->maccfg1); in init()
367 if (cfg->tx_pause_time) in init()
368 tmp |= cfg->tx_pause_time; in init()
369 if (cfg->tx_pause_time_extd) in init()
370 tmp |= cfg->tx_pause_time_extd << PTV_PTE_SHIFT; in init()
371 iowrite32be(tmp, ®s->ptv); in init()
374 tmp |= (cfg->rx_prepend << RCTRL_PAL_SHIFT) & RCTRL_PAL_MASK; in init()
378 iowrite32be(tmp, ®s->rctrl); in init()
384 iowrite32be(tbi_addr, ®s->tbipa); in init()
386 iowrite32be(0, ®s->tmr_ctrl); in init()
388 if (cfg->ptp_tsu_en) { in init()
391 iowrite32be(tmp, ®s->tmr_pevent); in init()
393 if (cfg->ptp_exception_en) { in init()
396 iowrite32be(tmp, ®s->tmr_pemask); in init()
403 iowrite32be(tmp, ®s->maccfg1); in init()
407 tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) & in init()
409 if (cfg->tx_pad_crc) in init()
411 iowrite32be(tmp, ®s->maccfg2); in init()
413 tmp = (((cfg->non_back_to_back_ipg1 << in init()
416 | ((cfg->non_back_to_back_ipg2 << in init()
419 | ((cfg->min_ifg_enforcement << IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT) in init()
421 | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG)); in init()
422 iowrite32be(tmp, ®s->ipgifg); in init()
426 tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT) in init()
428 tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW); in init()
430 iowrite32be(tmp, ®s->hafdup); in init()
433 iowrite32be(cfg->maximum_frame, ®s->maxfrm); in init()
435 iowrite32be(0xffffffff, ®s->cam1); in init()
436 iowrite32be(0xffffffff, ®s->cam2); in init()
438 iowrite32be(exception_mask, ®s->imask); in init()
440 iowrite32be(0xffffffff, ®s->ievent); in init()
450 iowrite32be(0, ®s->igaddr[i]); in init()
452 iowrite32be(0, ®s->gaddr[i]); in init()
467 reg = ®s->gaddr[reg_idx - 8]; in set_bucket()
469 reg = ®s->igaddr[reg_idx]; in set_bucket()
479 if ((dtsec->dtsec_drv_param)->rx_prepend > in check_init_parameters()
483 return -EINVAL; in check_init_parameters()
485 if (((dtsec->dtsec_drv_param)->non_back_to_back_ipg1 > in check_init_parameters()
487 ((dtsec->dtsec_drv_param)->non_back_to_back_ipg2 > in check_init_parameters()
489 ((dtsec->dtsec_drv_param)->back_to_back_ipg > in check_init_parameters()
493 return -EINVAL; in check_init_parameters()
495 if ((dtsec->dtsec_drv_param)->halfdup_retransmit > in check_init_parameters()
499 return -EINVAL; in check_init_parameters()
501 if ((dtsec->dtsec_drv_param)->halfdup_coll_window > in check_init_parameters()
505 return -EINVAL; in check_init_parameters()
510 if (!dtsec->exception_cb) { in check_init_parameters()
512 return -EINVAL; in check_init_parameters()
514 if (!dtsec->event_cb) { in check_init_parameters()
516 return -EINVAL; in check_init_parameters()
582 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_get_max_frame_length()
584 return (u16)ioread32be(®s->maxfrm); in dtsec_get_max_frame_length()
590 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_isr()
594 event = ioread32be(®s->ievent) & in dtsec_isr()
597 event &= ioread32be(®s->imask); in dtsec_isr()
599 iowrite32be(event, ®s->ievent); in dtsec_isr()
602 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_RX); in dtsec_isr()
604 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_RX_CTL); in dtsec_isr()
606 dtsec->exception_cb(dtsec->dev_id, in dtsec_isr()
609 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_TX); in dtsec_isr()
611 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_CTL); in dtsec_isr()
613 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_ERR); in dtsec_isr()
615 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_LATE_COL); in dtsec_isr()
617 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT); in dtsec_isr()
621 if (dtsec->fm_rev_info.major == 2) { in dtsec_isr()
627 tpkt1 = ioread32be(®s->tpkt); in dtsec_isr()
630 tmp_reg1 = ioread32be(®s->reserved02c0[27]); in dtsec_isr()
651 tpkt2 = ioread32be(®s->tpkt); in dtsec_isr()
652 tmp_reg2 = ioread32be(®s->reserved02c0[27]); in dtsec_isr()
668 iowrite32be(ioread32be(®s->rctrl) | in dtsec_isr()
669 RCTRL_GRS, ®s->rctrl); in dtsec_isr()
675 if (ioread32be(®s->ievent) & in dtsec_isr()
680 if (ioread32be(®s->ievent) & in dtsec_isr()
683 ®s->ievent); in dtsec_isr()
685 pr_debug("Rx lockup due to Tx lockup\n"); in dtsec_isr()
690 fman_reset_mac(dtsec->fm, dtsec->mac_id); in dtsec_isr()
701 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_FIFO_UNDRN); in dtsec_isr()
704 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_MAG_PCKT); in dtsec_isr()
706 dtsec->exception_cb(dtsec->dev_id, in dtsec_isr()
709 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_DATA_ERR); in dtsec_isr()
711 dtsec->exception_cb(dtsec->dev_id, FM_MAC_1G_RX_DATA_ERR); in dtsec_isr()
721 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_1588_isr()
724 if (dtsec->ptp_tsu_enabled) { in dtsec_1588_isr()
725 event = ioread32be(®s->tmr_pevent); in dtsec_1588_isr()
726 event &= ioread32be(®s->tmr_pemask); in dtsec_1588_isr()
729 iowrite32be(event, ®s->tmr_pevent); in dtsec_1588_isr()
731 dtsec->exception_cb(dtsec->dev_id, in dtsec_1588_isr()
739 fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, in free_init_resources()
741 fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, in free_init_resources()
745 free_hash_table(dtsec->multicast_addr_hash); in free_init_resources()
746 dtsec->multicast_addr_hash = NULL; in free_init_resources()
749 free_hash_table(dtsec->unicast_addr_hash); in free_init_resources()
750 dtsec->unicast_addr_hash = NULL; in free_init_resources()
753 static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs) in pcs_to_dtsec() argument
755 return container_of(pcs, struct fman_mac, pcs); in pcs_to_dtsec()
758 static void dtsec_pcs_get_state(struct phylink_pcs *pcs, in dtsec_pcs_get_state() argument
761 struct fman_mac *dtsec = pcs_to_dtsec(pcs); in dtsec_pcs_get_state()
763 phylink_mii_c22_pcs_get_state(dtsec->tbidev, state); in dtsec_pcs_get_state()
766 static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, in dtsec_pcs_config() argument
771 struct fman_mac *dtsec = pcs_to_dtsec(pcs); in dtsec_pcs_config()
773 return phylink_mii_c22_pcs_config(dtsec->tbidev, interface, in dtsec_pcs_config()
777 static void dtsec_pcs_an_restart(struct phylink_pcs *pcs) in dtsec_pcs_an_restart() argument
779 struct fman_mac *dtsec = pcs_to_dtsec(pcs); in dtsec_pcs_an_restart()
781 phylink_mii_c22_pcs_an_restart(dtsec->tbidev); in dtsec_pcs_an_restart()
792 struct dtsec_regs __iomem *regs = dtsec->regs; in graceful_start()
794 iowrite32be(ioread32be(®s->tctrl) & ~TCTRL_GTS, ®s->tctrl); in graceful_start()
795 iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_GRS, ®s->rctrl); in graceful_start()
800 struct dtsec_regs __iomem *regs = dtsec->regs; in graceful_stop()
803 /* Graceful stop - Assert the graceful Rx stop bit */ in graceful_stop()
804 tmp = ioread32be(®s->rctrl) | RCTRL_GRS; in graceful_stop()
805 iowrite32be(tmp, ®s->rctrl); in graceful_stop()
807 if (dtsec->fm_rev_info.major == 2) { in graceful_stop()
815 /* Graceful stop - Assert the graceful Tx stop bit */ in graceful_stop()
816 if (dtsec->fm_rev_info.major == 2) { in graceful_stop()
820 tmp = ioread32be(®s->tctrl) | TCTRL_GTS; in graceful_stop()
821 iowrite32be(tmp, ®s->tctrl); in graceful_stop()
842 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_set_tx_pause_frames()
847 if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) { in dtsec_set_tx_pause_frames()
848 pr_warn("pause-time: %d illegal.Should be > 320\n", in dtsec_set_tx_pause_frames()
850 return -EINVAL; in dtsec_set_tx_pause_frames()
853 ptv = ioread32be(®s->ptv); in dtsec_set_tx_pause_frames()
856 iowrite32be(ptv, ®s->ptv); in dtsec_set_tx_pause_frames()
858 /* trigger the transmission of a flow-control pause frame */ in dtsec_set_tx_pause_frames()
859 iowrite32be(ioread32be(®s->maccfg1) | MACCFG1_TX_FLOW, in dtsec_set_tx_pause_frames()
860 ®s->maccfg1); in dtsec_set_tx_pause_frames()
862 iowrite32be(ioread32be(®s->maccfg1) & ~MACCFG1_TX_FLOW, in dtsec_set_tx_pause_frames()
863 ®s->maccfg1); in dtsec_set_tx_pause_frames()
870 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_accept_rx_pause_frames()
873 tmp = ioread32be(®s->maccfg1); in dtsec_accept_rx_pause_frames()
878 iowrite32be(tmp, ®s->maccfg1); in dtsec_accept_rx_pause_frames()
886 struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac; in dtsec_select_pcs()
892 return &dtsec->pcs; in dtsec_select_pcs()
902 struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs; in dtsec_mac_config()
905 switch (state->interface) { in dtsec_mac_config()
921 dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n", in dtsec_mac_config()
922 phy_modes(state->interface)); in dtsec_mac_config()
926 iowrite32be(tmp, ®s->ecntrl); in dtsec_mac_config()
934 struct fman_mac *dtsec = mac_dev->fman_mac; in dtsec_link_up()
935 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_link_up()
943 tmp = ioread32be(®s->ecntrl); in dtsec_link_up()
948 iowrite32be(tmp, ®s->ecntrl); in dtsec_link_up()
950 tmp = ioread32be(®s->maccfg2); in dtsec_link_up()
960 iowrite32be(tmp, ®s->maccfg2); in dtsec_link_up()
962 mac_dev->update_speed(mac_dev, speed); in dtsec_link_up()
965 tmp = ioread32be(®s->maccfg1); in dtsec_link_up()
967 iowrite32be(tmp, ®s->maccfg1); in dtsec_link_up()
969 /* Graceful start - clear the graceful Rx/Tx stop bit */ in dtsec_link_up()
976 struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac; in dtsec_link_down()
977 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_link_down()
980 /* Graceful stop - Assert the graceful Rx/Tx stop bit */ in dtsec_link_down()
983 tmp = ioread32be(®s->maccfg1); in dtsec_link_down()
985 iowrite32be(tmp, ®s->maccfg1); in dtsec_link_down()
1003 dtsec->addr = ENET_ADDR_TO_UINT64(*enet_addr); in dtsec_modify_mac_address()
1004 set_mac_address(dtsec->regs, (const u8 *)(*enet_addr)); in dtsec_modify_mac_address()
1014 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_add_hash_mac_address()
1023 ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? true : false); in dtsec_add_hash_mac_address()
1029 return -EINVAL; in dtsec_add_hash_mac_address()
1055 set_bucket(dtsec->regs, bucket, true); in dtsec_add_hash_mac_address()
1060 return -ENOMEM; in dtsec_add_hash_mac_address()
1061 hash_entry->addr = addr; in dtsec_add_hash_mac_address()
1062 INIT_LIST_HEAD(&hash_entry->node); in dtsec_add_hash_mac_address()
1066 list_add_tail(&hash_entry->node, in dtsec_add_hash_mac_address()
1067 &dtsec->multicast_addr_hash->lsts[bucket]); in dtsec_add_hash_mac_address()
1069 list_add_tail(&hash_entry->node, in dtsec_add_hash_mac_address()
1070 &dtsec->unicast_addr_hash->lsts[bucket]); in dtsec_add_hash_mac_address()
1078 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_set_allmulti()
1080 tmp = ioread32be(®s->rctrl); in dtsec_set_allmulti()
1086 iowrite32be(tmp, ®s->rctrl); in dtsec_set_allmulti()
1093 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_set_tstamp()
1096 rctrl = ioread32be(®s->rctrl); in dtsec_set_tstamp()
1097 tctrl = ioread32be(®s->tctrl); in dtsec_set_tstamp()
1107 iowrite32be(rctrl, ®s->rctrl); in dtsec_set_tstamp()
1108 iowrite32be(tctrl, ®s->tctrl); in dtsec_set_tstamp()
1116 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_del_hash_mac_address()
1126 ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? true : false); in dtsec_del_hash_mac_address()
1132 return -EINVAL; in dtsec_del_hash_mac_address()
1151 &dtsec->multicast_addr_hash->lsts[bucket]) { in dtsec_del_hash_mac_address()
1153 if (hash_entry && hash_entry->addr == addr) { in dtsec_del_hash_mac_address()
1154 list_del_init(&hash_entry->node); in dtsec_del_hash_mac_address()
1159 if (list_empty(&dtsec->multicast_addr_hash->lsts[bucket])) in dtsec_del_hash_mac_address()
1160 set_bucket(dtsec->regs, bucket, false); in dtsec_del_hash_mac_address()
1164 &dtsec->unicast_addr_hash->lsts[bucket]) { in dtsec_del_hash_mac_address()
1166 if (hash_entry && hash_entry->addr == addr) { in dtsec_del_hash_mac_address()
1167 list_del_init(&hash_entry->node); in dtsec_del_hash_mac_address()
1172 if (list_empty(&dtsec->unicast_addr_hash->lsts[bucket])) in dtsec_del_hash_mac_address()
1173 set_bucket(dtsec->regs, bucket, false); in dtsec_del_hash_mac_address()
1184 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_set_promiscuous()
1188 tmp = ioread32be(®s->rctrl); in dtsec_set_promiscuous()
1194 iowrite32be(tmp, ®s->rctrl); in dtsec_set_promiscuous()
1197 tmp = ioread32be(®s->rctrl); in dtsec_set_promiscuous()
1203 iowrite32be(tmp, ®s->rctrl); in dtsec_set_promiscuous()
1211 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_set_exception()
1218 dtsec->exceptions |= bit_mask; in dtsec_set_exception()
1220 dtsec->exceptions &= ~bit_mask; in dtsec_set_exception()
1223 return -EINVAL; in dtsec_set_exception()
1226 iowrite32be(ioread32be(®s->imask) | bit_mask, in dtsec_set_exception()
1227 ®s->imask); in dtsec_set_exception()
1229 iowrite32be(ioread32be(®s->imask) & ~bit_mask, in dtsec_set_exception()
1230 ®s->imask); in dtsec_set_exception()
1232 if (!dtsec->ptp_tsu_enabled) { in dtsec_set_exception()
1234 return -EINVAL; in dtsec_set_exception()
1239 dtsec->en_tsu_err_exception = true; in dtsec_set_exception()
1240 iowrite32be(ioread32be(®s->tmr_pemask) | in dtsec_set_exception()
1242 ®s->tmr_pemask); in dtsec_set_exception()
1244 dtsec->en_tsu_err_exception = false; in dtsec_set_exception()
1245 iowrite32be(ioread32be(®s->tmr_pemask) & in dtsec_set_exception()
1247 ®s->tmr_pemask); in dtsec_set_exception()
1252 return -EINVAL; in dtsec_set_exception()
1261 struct dtsec_regs __iomem *regs = dtsec->regs; in dtsec_init()
1267 (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) { in dtsec_init()
1269 return -EINVAL; in dtsec_init()
1276 dtsec_drv_param = dtsec->dtsec_drv_param; in dtsec_init()
1278 err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if, in dtsec_init()
1279 dtsec->max_speed, dtsec->addr, dtsec->exceptions, in dtsec_init()
1280 dtsec->tbidev->addr); in dtsec_init()
1289 mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon); in dtsec_init()
1292 mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon); in dtsec_init()
1295 max_frm_ln = (u16)ioread32be(®s->maxfrm); in dtsec_init()
1296 err = fman_set_mac_max_frame(dtsec->fm, dtsec->mac_id, max_frm_ln); in dtsec_init()
1300 return -EINVAL; in dtsec_init()
1303 dtsec->multicast_addr_hash = in dtsec_init()
1305 if (!dtsec->multicast_addr_hash) { in dtsec_init()
1308 return -ENOMEM; in dtsec_init()
1311 dtsec->unicast_addr_hash = alloc_hash_table(DTSEC_HASH_TABLE_SIZE); in dtsec_init()
1312 if (!dtsec->unicast_addr_hash) { in dtsec_init()
1315 return -ENOMEM; in dtsec_init()
1319 fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, in dtsec_init()
1322 fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id, in dtsec_init()
1326 dtsec->dtsec_drv_param = NULL; in dtsec_init()
1335 kfree(dtsec->dtsec_drv_param); in dtsec_free()
1336 dtsec->dtsec_drv_param = NULL; in dtsec_free()
1337 if (!IS_ERR_OR_NULL(dtsec->tbidev)) in dtsec_free()
1338 put_device(&dtsec->tbidev->dev); in dtsec_free()
1361 dtsec->dtsec_drv_param = dtsec_drv_param; in dtsec_config()
1365 dtsec->regs = mac_dev->vaddr; in dtsec_config()
1366 dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr); in dtsec_config()
1367 dtsec->phy_if = mac_dev->phy_if; in dtsec_config()
1368 dtsec->mac_id = params->mac_id; in dtsec_config()
1369 dtsec->exceptions = (DTSEC_IMASK_BREN | in dtsec_config()
1382 dtsec->exception_cb = params->exception_cb; in dtsec_config()
1383 dtsec->event_cb = params->event_cb; in dtsec_config()
1384 dtsec->dev_id = mac_dev; in dtsec_config()
1385 dtsec->ptp_tsu_enabled = dtsec->dtsec_drv_param->ptp_tsu_en; in dtsec_config()
1386 dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en; in dtsec_config()
1388 dtsec->fm = params->fm; in dtsec_config()
1391 fman_get_revision(dtsec->fm, &dtsec->fm_rev_info); in dtsec_config()
1410 mac_dev->phylink_ops = &dtsec_mac_ops; in dtsec_initialization()
1411 mac_dev->set_promisc = dtsec_set_promiscuous; in dtsec_initialization()
1412 mac_dev->change_addr = dtsec_modify_mac_address; in dtsec_initialization()
1413 mac_dev->add_hash_mac_addr = dtsec_add_hash_mac_address; in dtsec_initialization()
1414 mac_dev->remove_hash_mac_addr = dtsec_del_hash_mac_address; in dtsec_initialization()
1415 mac_dev->set_exception = dtsec_set_exception; in dtsec_initialization()
1416 mac_dev->set_allmulti = dtsec_set_allmulti; in dtsec_initialization()
1417 mac_dev->set_tstamp = dtsec_set_tstamp; in dtsec_initialization()
1418 mac_dev->set_multi = fman_set_multi; in dtsec_initialization()
1419 mac_dev->enable = dtsec_enable; in dtsec_initialization()
1420 mac_dev->disable = dtsec_disable; in dtsec_initialization()
1422 mac_dev->fman_mac = dtsec_config(mac_dev, params); in dtsec_initialization()
1423 if (!mac_dev->fman_mac) { in dtsec_initialization()
1424 err = -EINVAL; in dtsec_initialization()
1428 dtsec = mac_dev->fman_mac; in dtsec_initialization()
1429 dtsec->dtsec_drv_param->maximum_frame = fman_get_max_frm(); in dtsec_initialization()
1430 dtsec->dtsec_drv_param->tx_pad_crc = true; in dtsec_initialization()
1432 phy_node = of_parse_phandle(mac_node, "tbi-handle", 0); in dtsec_initialization()
1435 err = -EINVAL; in dtsec_initialization()
1436 dev_err_probe(mac_dev->dev, err, in dtsec_initialization()
1437 "TBI PCS node is not available\n"); in dtsec_initialization()
1441 dtsec->tbidev = of_mdio_find_device(phy_node); in dtsec_initialization()
1443 if (!dtsec->tbidev) { in dtsec_initialization()
1444 err = -EPROBE_DEFER; in dtsec_initialization()
1445 dev_err_probe(mac_dev->dev, err, in dtsec_initialization()
1446 "could not find mdiodev for PCS\n"); in dtsec_initialization()
1449 dtsec->pcs.ops = &dtsec_pcs_ops; in dtsec_initialization()
1450 dtsec->pcs.neg_mode = true; in dtsec_initialization()
1451 dtsec->pcs.poll = true; in dtsec_initialization()
1453 supported = mac_dev->phylink_config.supported_interfaces; in dtsec_initialization()
1459 if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII || in dtsec_initialization()
1460 mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) { in dtsec_initialization()
1463 } else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) { in dtsec_initialization()
1467 if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) { in dtsec_initialization()
1474 * in-tree support for ethernet on these platforms... in dtsec_initialization()
1483 mac_dev->phylink_config.mac_capabilities = capabilities; in dtsec_initialization()
1494 dev_info(mac_dev->dev, "FMan dTSEC version: 0x%08x\n", in dtsec_initialization()
1495 ioread32be(&dtsec->regs->tsec_id)); in dtsec_initialization()