ethernet/freescale/fec.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
45 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
46 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
51 #define FEC_RXIC0		0x100 /* Rx Interrupt Coalescing for ring 0 */
52 #define FEC_RXIC1		0x104 /* Rx Interrupt Coalescing for ring 1 */
53 #define FEC_RXIC2		0x108 /* Rx Interrupt Coalescing for ring 2 */
80 #define FEC_R_DES_ACTIVE_1	0x1e0 /* Rx descriptor active for ring 1 */
82 #define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */
124 #define RMON_R_PACKETS		0x284 /* RMON RX packet count */
125 #define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
126 #define RMON_R_MC_PKT		0x28c /* RMON RX multicast pkts */
127 #define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
128 #define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
129 #define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
130 #define RMON_R_FRAG		0x29c /* RMON RX pkts < 64 bytes, bad CRC */
131 #define RMON_R_JAB		0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
133 #define RMON_R_P64		0x2a8 /* RMON RX 64 byte pkts */
134 #define RMON_R_P65TO127		0x2ac /* RMON RX 65 to 127 byte pkts */
135 #define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
136 #define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
137 #define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
138 #define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
139 #define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
140 #define RMON_R_OCTETS		0x2c4 /* RMON RX octets */
142 #define IEEE_R_FRAME_OK		0x2cc /* Frames rx'd OK */
143 #define IEEE_R_CRC		0x2d0 /* Frames rx'd with CRC err */
144 #define IEEE_R_ALIGN		0x2d4 /* Frames rx'd with alignment err */
146 #define IEEE_R_FDXFC		0x2dc /* Flow control pause frames rx'd */
147 #define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
170 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
171 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
309  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
344 /* The number of Tx and Rx buffers.  These are allocated from the page
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
410 /* Controller is ENET-MAC */
430  * frames not being transmitted until there is a 0-to-1 transition on
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
493  * standard. For the transmission, MAC supply two user registers to set
518 	/* Address of Rx and Tx buffers */
581 	/* rx queue number, in the range 0-7 */
605 	struct clk *clk_ipg;
606 	struct clk *clk_ahb;
607 	struct clk *clk_ref;
608 	struct clk *clk_enet_out;
609 	struct clk *clk_ptp;
610 	struct clk *clk_2x_txclk;
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */