ethernet/freescale/fec.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
309  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
399 /* ENET interrupt coalescing macro define */
410 /* Controller is ENET-MAC */
424 /* ENET IP errata ERR006358
430  * frames not being transmitted until there is a 0-to-1 transition on
434 /* ENET IP hw AVB
436  * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
447  * The issue exist at i.MX6SX enet IP.
450 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
487 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
488  * represents this ENET IP.
492 /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
498 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
500  * For the implementation of delayed clock, ENET takes synchronized 250MHz
581 	/* rx queue number, in the range 0-7 */
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */