ethernet/freescale/fec.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
47 #define FEC_OPD			0x0ec /* Opcode + Pause duration */
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
410 /* Controller is ENET-MAC */
430  * frames not being transmitted until there is a 0-to-1 transition on
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
452  * value is capture in the register clock domain.
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
454  * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
456  * (40ns * 6).
500  * For the implementation of delayed clock, ENET takes synchronized 250MHz
501  * clocks to generate 2ns delay.
581 	/* rx queue number, in the range 0-7 */
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
678 	/* ptp clock period in ns*/