185 		buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;  in nps_enet_poll()
186 		buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;  in nps_enet_poll()
274 	ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;  in nps_enet_hw_reset()
281 	phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;  in nps_enet_hw_reset()
282 	phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;  in nps_enet_hw_reset()
305 		 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;  in nps_enet_hw_enable_control()
309 		 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;  in nps_enet_hw_enable_control()
323 	buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;  in nps_enet_hw_enable_control()
324 	buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;  in nps_enet_hw_enable_control()
332 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;  in nps_enet_hw_enable_control()
333 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;  in nps_enet_hw_enable_control()
334 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;  in nps_enet_hw_enable_control()
343 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;  in nps_enet_hw_enable_control()
348 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;  in nps_enet_hw_enable_control()
349 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;  in nps_enet_hw_enable_control()
353 		 | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;  in nps_enet_hw_enable_control()
356 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;  in nps_enet_hw_enable_control()
357 	ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;  in nps_enet_hw_enable_control()
397 	tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;  in nps_enet_send_frame()
449 			 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;  in nps_enet_set_rx_mode()
451 			 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;  in nps_enet_set_rx_mode()