Lines Matching +full:post +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
129 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
136 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
139 /* Rearm to interrupt delay encoding */
140 #define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */
142 /* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
144 * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
147 #define R2I_DLY_ENC_0 0 /* No delay */
148 #define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */
149 #define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */
150 #define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */
154 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
155 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
156 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
157 placing at 11-15 */
160 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
166 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
168 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
169 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
173 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
175 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
179 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
181 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
202 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
215 __le32 frag_len; /* dword 3: bits 0 - 15 */