Lines Matching full:gmac

2 /* Register definitions for Gemini GMAC Ethernet device driver
49  *		GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
91 /* GMAC 0/1 DMA/TOE register */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
148 /* TOE GMAC 0/1 register */
332 /* GMAC DMA Control Register
366 /* GMAC Tx Weighting Control Register 0
386 /* GMAC Tx Weighting Control Register 1
410 /* GMAC DMA Tx Description Word 0 Register
434 /* GMAC DMA Tx Description Word 1 Register
474 /* GMAC DMA Tx Description Word 2 Register
483 /* GMAC DMA Tx Description Word 3 Register
507 /* GMAC Tx Descriptor */
515 /* GMAC DMA Rx Description Word 0 Register
581 /* GMAC DMA Rx Description Word 1 Register
595 /* GMAC DMA Rx Description Word 2 Register
609 /* GMAC DMA Rx Description Word 3 Register
639 /* GMAC Rx Descriptor, this is simply fitted over the queue registers */
647 /* GMAC Matching Rule Control Register 0
691 /* GMAC RX FLTR
716 /* GMAC Configuration 0
796 /* GMAC Configuration 1
816 /* GMAC Configuration 2
830 /* GMAC Configuration 3
844 /* GMAC STATUS