Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
57 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
91 /* GMAC 0/1 DMA/TOE register */
148 /* TOE GMAC 0/1 register */
165 #define GMAC_IN_MAC1 0x0040 /* for STA 1 MAC Address */
200 #define GMAC1_TXDERR_INT_BIT BIT(31)
201 #define GMAC1_TXPERR_INT_BIT BIT(30)
202 #define GMAC0_TXDERR_INT_BIT BIT(29)
203 #define GMAC0_TXPERR_INT_BIT BIT(28)
204 #define GMAC1_RXDERR_INT_BIT BIT(27)
205 #define GMAC1_RXPERR_INT_BIT BIT(26)
206 #define GMAC0_RXDERR_INT_BIT BIT(25)
207 #define GMAC0_RXPERR_INT_BIT BIT(24)
208 #define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
209 #define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
210 #define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
211 #define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
212 #define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
213 #define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
214 #define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
215 #define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
216 #define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
217 #define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
218 #define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
219 #define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
220 #define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
221 #define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
222 #define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
223 #define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
224 #define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
225 #define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
226 #define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
227 #define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
228 #define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
229 #define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
230 #define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
231 #define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
233 /* Interrupt Status Register 1 (offset 0x0030)
234 * Interrupt Mask Register 1 (offset 0x0034)
235 * Interrupt Select Register 1 (offset 0x0038)
237 #define TOE_IQ3_FULL_INT_BIT BIT(31)
238 #define TOE_IQ2_FULL_INT_BIT BIT(30)
239 #define TOE_IQ1_FULL_INT_BIT BIT(29)
240 #define TOE_IQ0_FULL_INT_BIT BIT(28)
241 #define TOE_IQ3_INT_BIT BIT(27)
242 #define TOE_IQ2_INT_BIT BIT(26)
243 #define TOE_IQ1_INT_BIT BIT(25)
244 #define TOE_IQ0_INT_BIT BIT(24)
245 #define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
246 #define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
247 #define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
248 #define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
249 #define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
250 #define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
251 #define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
252 #define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
253 #define CLASS_RX_INT_BIT(x) BIT((x + 2))
254 #define DEFAULT_Q1_INT_BIT BIT(1)
255 #define DEFAULT_Q0_INT_BIT BIT(0)
268 #define TOE_QL_FULL_INT_BIT(x) BIT(x)
274 #define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
280 #define GMAC1_RESERVED_INT_BIT BIT(31)
281 #define GMAC1_MIB_INT_BIT BIT(30)
282 #define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
283 #define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
284 #define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
285 #define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
286 #define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
287 #define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
288 #define GMAC0_RESERVED_INT_BIT BIT(23)
289 #define GMAC0_MIB_INT_BIT BIT(22)
290 #define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
291 #define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
292 #define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
293 #define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
294 #define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
295 #define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
296 #define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2)
297 #define HWFQ_EMPTY_INT_BIT BIT(1)
298 #define SWFQ_EMPTY_INT_BIT BIT(0)
339 /* bit 1:0 Peripheral Bus Width */
341 /* bit 3:2 TxDMA max burst size for every AHB request */
343 /* bit 7:4 TxDMA protection control */
345 /* bit 9:8 Peripheral Bus Width */
347 /* bit 11:10 DMA max burst size for every AHB request */
349 /* bit 15:12 DMA Protection Control */
351 /* bit 17:16 */
353 /* bit 27:18 */
355 /* bit 28 1: Drop, 0: Accept */
356 unsigned int drop_small_ack:1;
357 /* bit 29 Loopback TxDMA to RxDMA */
358 unsigned int loopback:1;
359 /* bit 30 Tx DMA Enable */
360 unsigned int td_enable:1;
361 /* bit 31 Rx DMA Enable */
362 unsigned int rd_enable:1;
373 /* bit 5:0 HW TX Queue 3 */
375 /* bit 11:6 HW TX Queue 2 */
377 /* bit 17:12 HW TX Queue 1 */
379 /* bit 23:18 HW TX Queue 0 */
381 /* bit 31:24 */
386 /* GMAC Tx Weighting Control Register 1
393 /* bit 4:0 SW TX Queue 0 */
395 /* bit 9:5 SW TX Queue 1 */
397 /* bit 14:10 SW TX Queue 2 */
399 /* bit 19:15 SW TX Queue 3 */
401 /* bit 24:20 SW TX Queue 4 */
403 /* bit 29:25 SW TX Queue 5 */
405 /* bit 31:30 */
417 /* bit 15:0 Transfer size */
419 /* bit 21:16 number of descriptors used for the current frame */
421 /* bit 22 Tx Status, 1: Successful 0: Failed */
422 unsigned int status_tx_ok:1;
423 /* bit 28:23 Tx Status, Reserved bits */
425 /* bit 29 protocol error during processing this descriptor */
426 unsigned int perr:1;
427 /* bit 30 data error during processing this descriptor */
428 unsigned int derr:1;
429 /* bit 31 */
430 unsigned int reserved:1;
434 /* GMAC DMA Tx Description Word 1 Register
441 /* bit 15: 0 Tx Frame Byte Count */
443 /* bit 16 TSS segmentation use MTU setting */
444 unsigned int mtu_enable:1;
445 /* bit 17 IPV4 Header Checksum Enable */
446 unsigned int ip_chksum:1;
447 /* bit 18 IPV6 Tx Enable */
448 unsigned int ipv6_enable:1;
449 /* bit 19 TCP Checksum Enable */
450 unsigned int tcp_chksum:1;
451 /* bit 20 UDP Checksum Enable */
452 unsigned int udp_chksum:1;
453 /* bit 21 Bypass HW offload engine */
454 unsigned int bypass_tss:1;
455 /* bit 22 Don't update IP length field */
456 unsigned int ip_fixed_len:1;
457 /* bit 31:23 Tx Flag, Reserved */
462 #define TSS_IP_FIXED_LEN_BIT BIT(22)
463 #define TSS_BYPASS_BIT BIT(21)
464 #define TSS_UDP_CHKSUM_BIT BIT(20)
465 #define TSS_TCP_CHKSUM_BIT BIT(19)
466 #define TSS_IPV6_ENABLE_BIT BIT(18)
467 #define TSS_IP_CHKSUM_BIT BIT(17)
468 #define TSS_MTU_ENABLE_BIT BIT(16)
490 /* bit 12: 0 Tx Frame Byte Count */
492 /* bit 28:13 */
494 /* bit 29 End of frame interrupt enable */
495 unsigned int eofie:1;
496 /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
504 #define EOFIE_BIT BIT(29)
522 /* bit 15:0 number of descriptors used for the current frame */
524 /* bit 21:16 number of descriptors used for the current frame */
526 /* bit 24:22 Status of rx frame */
528 /* bit 28:26 Check Sum Status */
530 /* bit 29 protocol error during processing this descriptor */
531 unsigned int perr:1;
532 /* bit 30 data error during processing this descriptor */
533 unsigned int derr:1;
534 /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
535 unsigned int drop:1;
539 #define GMAC_RXDESC_0_T_derr BIT(30)
540 #define GMAC_RXDESC_0_T_perr BIT(29)
541 #define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26)
542 #define GMAC_RXDESC_0_T_status(x) BIT(x + 22)
543 #define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16)
546 #define RX_CHKSUM_IP_OK_ONLY 1
554 #define RX_STATUS_TOO_LONG_GOOD_CRC 1
581 /* GMAC DMA Rx Description Word 1 Register
588 /* bit 15: 0 Rx Frame Byte Count */
590 /* bit 31:16 Software ID */
605 #define RX_INSERT_1_BYTE 1
616 /* bit 7: 0 L3 data offset */
618 /* bit 15: 8 L4 data offset */
620 /* bit 23: 16 L7 data offset */
622 /* bit 24 Duplicated ACK detected */
623 unsigned int dup_ack:1;
624 /* bit 25 abnormal case found */
625 unsigned int abnormal:1;
626 /* bit 26 IPV4 option or IPV6 extension header */
627 unsigned int option:1;
628 /* bit 27 Out of Sequence packet */
629 unsigned int out_of_seq:1;
630 /* bit 28 Control Flag is present */
631 unsigned int ctrl_flag:1;
632 /* bit 29 End of frame interrupt enable */
633 unsigned int eofie:1;
634 /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
651 #define MR_L2_BIT BIT(31)
652 #define MR_L3_BIT BIT(30)
653 #define MR_L4_BIT BIT(29)
654 #define MR_L7_BIT BIT(28)
655 #define MR_PORT_BIT BIT(27)
656 #define MR_PRIORITY_BIT BIT(26)
657 #define MR_DA_BIT BIT(23)
658 #define MR_SA_BIT BIT(22)
659 #define MR_ETHER_TYPE_BIT BIT(21)
660 #define MR_VLAN_BIT BIT(20)
661 #define MR_PPPOE_BIT BIT(19)
662 #define MR_IP_VER_BIT BIT(15)
663 #define MR_IP_HDR_LEN_BIT BIT(14)
664 #define MR_FLOW_LABLE_BIT BIT(13)
665 #define MR_TOS_TRAFFIC_BIT BIT(12)
666 #define MR_SPR_BIT(x) BIT(x)
701 unsigned int unicast:1;
705 unsigned int multicast:1;
707 unsigned int broadcast:1;
709 unsigned int promiscuous:1;
711 unsigned int error:1;
724 unsigned int dis_tx:1;
725 /* 1: disable receive */
726 unsigned int dis_rx:1;
728 unsigned int loop_back:1;
730 unsigned int flow_ctrl:1;
731 /* 4-7: adjust IFG from 96+/-56 */
733 /* 8-10 maximum receive frame length allowed */
735 /* 11: disable back-off function */
736 unsigned int dis_bkoff:1;
738 unsigned int dis_col:1;
740 unsigned int sim_test:1;
742 unsigned int rx_fc_en:1;
744 unsigned int tx_fc_en:1;
745 /* 16: RGMII in-band status enable */
746 unsigned int rgmii_en:1;
748 unsigned int ipv4_rx_chksum:1;
750 unsigned int ipv6_rx_chksum:1;
752 unsigned int rx_tag_remove:1;
754 unsigned int rgmm_edge:1;
756 unsigned int rxc_inv:1;
758 unsigned int ipv6_exthdr_order:1;
760 unsigned int rx_err_detect:1;
762 unsigned int port0_chk_hwq:1;
764 unsigned int port1_chk_hwq:1;
766 unsigned int port0_chk_toeq:1;
768 unsigned int port1_chk_toeq:1;
770 unsigned int port0_chk_classq:1;
772 unsigned int port1_chk_classq:1;
778 #define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0))
779 #define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17))
780 #define CONFIG0_FLOW_RX BIT(14)
781 #define CONFIG0_FLOW_TX BIT(15)
782 #define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15))
783 #define CONFIG0_FLOW_CTL (BIT(14) | BIT(15))
788 #define CONFIG0_MAXLEN_1518 1
796 /* GMAC Configuration 1
852 unsigned int link:1;
853 /* Link speed(00->2.5M 01->25M 10->125M) */
856 unsigned int duplex:1;
857 unsigned int reserved_1:1;
865 #define GMAC_SPEED_100 1
869 #define GMAC_PHY_GMII 1
874 * (1) TOE Queue Header
875 * (2) Non-TOE Queue Header
880 * 0x60003000 +---------------------------+ 0x0000
883 * +---------------------------+ 0x0020
884 * | TOE Queue 1 Header |
886 * +---------------------------+ 0x0040
889 * +---------------------------+
892 * 0x60002000 +---------------------------+ 0x0000
895 * +---------------------------+ 0x0008
896 * | Default Queue 1 Header |
898 * +---------------------------+ 0x0010
901 * +---------------------------+
902 * | Classification Queue 1 |
904 * +---------------------------+ (n * 8 + 0x10)
907 * +---------------------------+ (13 * 8 + 0x10)
910 * +---------------------------+ 0x80
913 * +---------------------------+
914 * | Interrupt Queue 1 |
916 * +---------------------------+
919 * +---------------------------+
922 * +---------------------------+
926 #define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
931 #define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
941 /* NONTOE Queue Header Word 1 */
945 /* bit 15:0 */
947 /* bit 31:16 */
952 /* Non-TOE Queue Header */