chelsio/cxgb4vf/adapter.h

2  * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
10  * COPYING in the main directory of this source tree, or the
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
54  * Constants of the implementation.
57 	MAX_NPORTS	= 1,		/* max # of "ports" */
58 	MAX_PORT_QSETS	= 8,		/* max # of Queue Sets / "port" */
62 	 * MSI-X interrupt index usage.
64 	MSIX_FW		= 0,		/* MSI-X index for firmware Q */
65 	MSIX_IQFLINT	= 1,		/* MSI-X index base for Ingress Qs */
70 	 * The maximum number of Ingress and Egress Queues is determined by
71 	 * the maximum number of "Queue Sets" which we support plus any
90  * Per-"port" information.  This is really per-Virtual Interface information
91  * but the use of the "port" nomanclature makes it easier to go back and forth
98 	int xact_addr_filt;		/* index of our MAC address filter */
99 	u16 rss_size;			/* size of VI's RSS table slice */
105 	u8 nqsets;			/* # of "Queue Sets" */
106 	u8 first_qset;			/* index of first "Queue Set" */
112  * queues are organized into "Queue Sets" with one ingress and one egress
113  * queue per Queue Set.  These Queue Sets are aportionable between the "ports"
116  * use here are really "Relative Queue IDs" which are returned as part of the
118  * absolute Queue ID base of the section of the Queue ID space allocated to
123  * SGE free-list queue state.
127 	unsigned int avail;		/* # of available RX buffers */
131 	unsigned long alloc_failed;	/* # of buffer allocation failures */
133 	unsigned long starving;		/* # of times FL was found starving */
136 	 * Write-once/infrequently fields.
137 	 * -------------------------------
142 	unsigned int size;		/* capacity of free list */
143 	struct rx_sw_desc *sdesc;	/* address of SW RX descriptor ring */
144 	__be64 *desc;			/* address of HW RX descriptor ring */
145 	dma_addr_t addr;		/* PCI bus address of hardware ring */
146 	void __iomem *bar2_addr;	/* address of BAR2 Queue registers */
155 	void *va;			/* virtual address of first byte */
156 	unsigned int nfrags;		/* # of fragments */
157 	unsigned int tot_len;		/* total length of fragments */
177 	 * Write-once/infrequently fields.
178 	 * -------------------------------
186 	__be64 *desc;			/* address of hardware response ring */
187 	dma_addr_t phys_addr;		/* PCI bus address of ring */
188 	void __iomem *bar2_addr;	/* address of BAR2 Queue registers */
191 	unsigned int size;		/* capcity of response Q */
201 	unsigned long pkts;		/* # of ethernet packets */
202 	unsigned long lro_pkts;		/* # of LRO super packets */
203 	unsigned long lro_merged;	/* # of wire packets merged by LRO */
204 	unsigned long rx_cso;		/* # of Rx checksum offloads */
205 	unsigned long vlan_ex;		/* # of Rx VLAN extractions */
206 	unsigned long rx_drops;		/* # of packets dropped due to no mem */
219  * SGE Transmit Queue state.  This contains all of the resources associated
220  * with the hardware status of a TX Queue which is a circular ring of hardware
227 	 * Egress Queues are measured in units of SGE_EQ_IDXSIZE by the
234 	unsigned int in_use;		/* # of in-use TX descriptors */
235 	unsigned int size;		/* # of descriptors */
238 	unsigned long stops;		/* # of times queue has been stopped */
239 	unsigned long restarts;		/* # of queue restarts */
242 	 * Write-once/infrequently fields.
243 	 * -------------------------------
248 	struct tx_desc *desc;		/* address of HW TX descriptor ring */
249 	struct tx_sw_desc *sdesc;	/* address of SW TX descriptor ring */
251 	dma_addr_t phys_addr;		/* PCI bus address of hardware ring */
252 	void __iomem *bar2_addr;	/* address of BAR2 Queue registers */
262 	unsigned long tso;		/* # of TSO requests */
263 	unsigned long tx_cso;		/* # of TX checksum offloads */
264 	unsigned long vlan_ins;		/* # of TX VLAN insertions */
265 	unsigned long mapping_err;	/* # of I/O MMU packet mapping errors */
269  * The complete set of Scatter/Gather Engine resources.
273 	 * Our "Queue Sets" ...
288 	 * State for managing "starving Free Lists" -- Free Lists which have
289 	 * fallen below a certain threshold of buffers available to the
303 	 * Write-once/infrequently fields.
304 	 * -------------------------------
307 	u16 max_ethqsets;		/* # of available Ethernet queue sets */
308 	u16 ethqsets;			/* # of active Ethernet queue sets */
316 	u32 stat_len;			/* length of status page at ring end */
337  * Utility macros to convert Absolute- to Relative-Queue indices and Egress-
338  * and Ingress-Queues.  The EQ_MAP() and IQ_MAP() macros which provide
339  * pointers to Ingress- and Egress-Queues can be used as both L- and R-values
341 #define EQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->egr_base))
342 #define IQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->ingr_base))
344 #define EQ_MAP(s, abs_id) ((s)->egr_map[EQ_IDX(s, abs_id)])
345 #define IQ_MAP(s, abs_id) ((s)->ingr_map[IQ_IDX(s, abs_id)])
348  * Macro to iterate across Queue Sets ("rxq" is a historic misnomer).
351 	for (iter = 0; iter < (sge)->ethqsets; iter++)
364  * Per-"adapter" (Virtual Function) information.
405 	/* list of MAC addresses in MPS Hash */
424  * t4_read_reg - read a HW register
428  * Returns the 32-bit value of the given HW register.
432 	return readl(adapter->regs + reg_addr);  in t4_read_reg()
436  * t4_write_reg - write a HW register
441  * Write a 32-bit value into the given HW register.
445 	writel(val, adapter->regs + reg_addr);  in t4_write_reg()
462  * t4_read_reg64 - read a 64-bit HW register
466  * Returns the 64-bit value of the given HW register.
470 	return readq(adapter->regs + reg_addr);  in t4_read_reg64()
474  * t4_write_reg64 - write a 64-bit HW register
479  * Write a 64-bit value into the given HW register.
484 	writeq(val, adapter->regs + reg_addr);  in t4_write_reg64()
488  * port_name - return the string name of a port
492  * Return the string name of the selected port.
496 	return adapter->port[pidx]->name;  in port_name()
500  * t4_os_set_hw_addr - store a port's MAC address in SW
505  * Store the Ethernet address of the given port in SW.  Called by the common
511 	eth_hw_addr_set(adapter->port[pidx], hw_addr);  in t4_os_set_hw_addr()
515  * netdev2pinfo - return the port_info structure associated with a net_device
526  * adap2pinfo - return the port_info of a port
534 	return netdev_priv(adapter->port[pidx]);  in adap2pinfo()
538  * netdev2adap - return the adapter structure associated with a net_device
545 	return netdev2pinfo(dev)->adapter;  in netdev2adap()