chelsio/cxgb4vf/adapter.h

2  * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17  *      - Redistributions of source code must retain the above
21  *      - Redistributions in binary form must reproduce the above
62 	 * MSI-X interrupt index usage.
64 	MSIX_FW		= 0,		/* MSI-X index for firmware Q */
65 	MSIX_IQFLINT	= 1,		/* MSI-X index base for Ingress Qs */
90  * Per-"port" information.  This is really per-Virtual Interface information
118  * absolute Queue ID base of the section of the Queue ID space allocated to
123  * SGE free-list queue state.
136 	 * Write-once/infrequently fields.
137 	 * -------------------------------
177 	 * Write-once/infrequently fields.
178 	 * -------------------------------
234 	unsigned int in_use;		/* # of in-use TX descriptors */
242 	 * Write-once/infrequently fields.
243 	 * -------------------------------
280 	 * forwarded interrupts (when in MSI mode).
288 	 * State for managing "starving Free Lists" -- Free Lists which have
303 	 * Write-once/infrequently fields.
304 	 * -------------------------------
324 	 * [potentially large] Base Queue ID.  We perform the reverse map by
326 	 * subtracting off the Base Queue ID and then use a Relative Queue ID
337  * Utility macros to convert Absolute- to Relative-Queue indices and Egress-
338  * and Ingress-Queues.  The EQ_MAP() and IQ_MAP() macros which provide
339  * pointers to Ingress- and Egress-Queues can be used as both L- and R-values
341 #define EQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->egr_base))
342 #define IQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->ingr_base))
344 #define EQ_MAP(s, abs_id) ((s)->egr_map[EQ_IDX(s, abs_id)])
345 #define IQ_MAP(s, abs_id) ((s)->ingr_map[IQ_IDX(s, abs_id)])
351 	for (iter = 0; iter < (sge)->ethqsets; iter++)
364  * Per-"adapter" (Virtual Function) information.
381 		unsigned short vec;  member
424  * t4_read_reg - read a HW register
428  * Returns the 32-bit value of the given HW register.
432 	return readl(adapter->regs + reg_addr);  in t4_read_reg()
436  * t4_write_reg - write a HW register
441  * Write a 32-bit value into the given HW register.
445 	writel(val, adapter->regs + reg_addr);  in t4_write_reg()
462  * t4_read_reg64 - read a 64-bit HW register
466  * Returns the 64-bit value of the given HW register.
470 	return readq(adapter->regs + reg_addr);  in t4_read_reg64()
474  * t4_write_reg64 - write a 64-bit HW register
479  * Write a 64-bit value into the given HW register.
484 	writeq(val, adapter->regs + reg_addr);  in t4_write_reg64()
488  * port_name - return the string name of a port
496 	return adapter->port[pidx]->name;  in port_name()
500  * t4_os_set_hw_addr - store a port's MAC address in SW
511 	eth_hw_addr_set(adapter->port[pidx], hw_addr);  in t4_os_set_hw_addr()
515  * netdev2pinfo - return the port_info structure associated with a net_device
526  * adap2pinfo - return the port_info of a port
534 	return netdev_priv(adapter->port[pidx]);  in adap2pinfo()
538  * netdev2adap - return the adapter structure associated with a net_device
545 	return netdev2pinfo(dev)->adapter;  in netdev2adap()