Lines Matching +full:0 +full:x9680
38 #define MYPF_BASE 0x1b000
41 #define PF0_BASE 0x1e000
44 #define PF_STRIDE 0x400
51 #define MYPORT_BASE 0x1c000
54 #define PORT0_BASE 0x20000
57 #define PORT_STRIDE 0x2000
74 #define SGE_PF_KDOORBELL_A 0x0
83 #define PIDX_S 0
86 #define SGE_VF_KDOORBELL_A 0x0
92 #define PIDX_T5_S 0
93 #define PIDX_T5_M 0x1fffU
97 #define SGE_PF_GTS_A 0x4
108 #define CIDXINC_S 0
109 #define CIDXINC_M 0xfffU
112 #define SGE_CONTROL_A 0x1008
113 #define SGE_CONTROL2_A 0x1124
124 #define PKTSHIFT_M 0x7U
132 #define INGPADBOUNDARY_M 0x7U
140 #define INGPACKBOUNDARY_M 0x7U
149 #define SGE_DBVFIFO_BADDR_A 0x1138
152 #define DBVFIFO_SIZE_M 0xfffU
155 #define T6_DBVFIFO_SIZE_S 0
156 #define T6_DBVFIFO_SIZE_M 0x1fffU
159 #define SGE_CTXT_CMD_A 0x11fc
166 #define CTXTTYPE_M 0x3U
169 #define CTXTQID_S 0
170 #define CTXTQID_M 0x1ffffU
173 #define SGE_CTXT_DATA0_A 0x1200
174 #define SGE_CTXT_DATA5_A 0x1214
176 #define GLOBALENABLE_S 0
180 #define SGE_HOST_PAGE_SIZE_A 0x100c
183 #define HOSTPAGESIZEPF7_M 0xfU
188 #define HOSTPAGESIZEPF6_M 0xfU
193 #define HOSTPAGESIZEPF5_M 0xfU
198 #define HOSTPAGESIZEPF4_M 0xfU
203 #define HOSTPAGESIZEPF3_M 0xfU
208 #define HOSTPAGESIZEPF2_M 0xfU
213 #define HOSTPAGESIZEPF1_M 0xfU
217 #define HOSTPAGESIZEPF0_S 0
218 #define HOSTPAGESIZEPF0_M 0xfU
222 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
223 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
227 #define QUEUESPERPAGEPF0_S 0
228 #define QUEUESPERPAGEPF0_M 0xfU
232 #define SGE_INT_CAUSE1_A 0x1024
233 #define SGE_INT_CAUSE2_A 0x1030
234 #define SGE_INT_CAUSE3_A 0x103c
332 #define SGE_INT_ENABLE3_A 0x1040
333 #define SGE_FL_BUFFER_SIZE0_A 0x1044
334 #define SGE_FL_BUFFER_SIZE1_A 0x1048
335 #define SGE_FL_BUFFER_SIZE2_A 0x104c
336 #define SGE_FL_BUFFER_SIZE3_A 0x1050
337 #define SGE_FL_BUFFER_SIZE4_A 0x1054
338 #define SGE_FL_BUFFER_SIZE5_A 0x1058
339 #define SGE_FL_BUFFER_SIZE6_A 0x105c
340 #define SGE_FL_BUFFER_SIZE7_A 0x1060
341 #define SGE_FL_BUFFER_SIZE8_A 0x1064
343 #define SGE_IMSG_CTXT_BADDR_A 0x1088
344 #define SGE_FLM_CACHE_BADDR_A 0x108c
345 #define SGE_FLM_CFG_A 0x1090
352 #define HDRSTARTFLQ_M 0x7U
355 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
358 #define THRESHOLD_0_M 0x3fU
363 #define THRESHOLD_1_M 0x3fU
368 #define THRESHOLD_2_M 0x3fU
372 #define THRESHOLD_3_S 0
373 #define THRESHOLD_3_M 0x3fU
377 #define SGE_CONM_CTRL_A 0x1094
380 #define EGRTHRESHOLD_M 0x3fU
385 #define EGRTHRESHOLDPACKING_M 0x3fU
391 #define T6_EGRTHRESHOLDPACKING_M 0xffU
395 #define SGE_TIMESTAMP_LO_A 0x1098
396 #define SGE_TIMESTAMP_HI_A 0x109c
399 #define TSOP_M 0x3U
403 #define TSVAL_S 0
404 #define TSVAL_M 0xfffffffU
408 #define SGE_DBFIFO_STATUS_A 0x10a4
409 #define SGE_DBVFIFO_SIZE_A 0x113c
412 #define HP_INT_THRESH_M 0xfU
416 #define LP_INT_THRESH_M 0xfU
419 #define SGE_DOORBELL_CONTROL_A 0x10a8
429 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
432 #define TIMERVALUE0_M 0xffffU
436 #define TIMERVALUE1_S 0
437 #define TIMERVALUE1_M 0xffffU
441 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
444 #define TIMERVALUE2_M 0xffffU
448 #define TIMERVALUE3_S 0
449 #define TIMERVALUE3_M 0xffffU
453 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
456 #define TIMERVALUE4_M 0xffffU
460 #define TIMERVALUE5_S 0
461 #define TIMERVALUE5_M 0xffffU
465 #define SGE_DEBUG_INDEX_A 0x10cc
466 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
467 #define SGE_DEBUG_DATA_LOW_A 0x10d4
469 #define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
470 #define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
471 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
473 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
474 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
476 #define SGE_ERROR_STATS_A 0x1100
486 #define ERROR_QID_S 0
487 #define ERROR_QID_M 0x1ffffU
490 #define SGE_INT_CAUSE5_A 0x110c
497 #define HP_INT_THRESH_M 0xfU
501 #define HP_COUNT_M 0x7ffU
505 #define LP_INT_THRESH_M 0xfU
508 #define LP_COUNT_S 0
509 #define LP_COUNT_M 0x7ffU
513 #define LP_INT_THRESH_T5_M 0xfffU
516 #define LP_COUNT_T5_S 0
517 #define LP_COUNT_T5_M 0x3ffffU
520 #define SGE_DOORBELL_CONTROL_A 0x10a8
522 #define SGE_STAT_TOTAL_A 0x10e4
523 #define SGE_STAT_MATCH_A 0x10e8
524 #define SGE_STAT_CFG_A 0x10ec
530 #define STATSOURCE_T5_M 0xfU
534 #define T6_STATMODE_S 0
537 #define SGE_DBFIFO_STATUS2_A 0x1118
540 #define HP_INT_THRESH_T5_M 0xfU
543 #define HP_COUNT_T5_S 0
544 #define HP_COUNT_T5_M 0x3ffU
551 #define DROPPED_DB_S 0
555 #define SGE_CTXT_CMD_A 0x11fc
556 #define SGE_DBQ_CTXT_BADDR_A 0x1084
559 #define PCIE_PF_CFG_A 0x40
562 #define AIVEC_M 0x3ffU
565 #define PCIE_PF_CLI_A 0x44
567 #define PCIE_PF_EXPROM_OFST_A 0x4c
569 #define OFFSET_M 0x3fffU
572 #define PCIE_INT_CAUSE_A 0x3004
690 #define MSIADDRLPERR_S 0
758 #define MSTGRPPERR_S 0
762 #define PCIE_NONFAT_ERR_A 0x3010
763 #define PCIE_CFG_SPACE_REQ_A 0x3060
764 #define PCIE_CFG_SPACE_DATA_A 0x3064
765 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
768 #define PCIEOFST_M 0x3fffffU
772 #define BIR_M 0x3U
776 #define WINDOW_S 0
777 #define WINDOW_M 0xffU
781 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
794 #define REGISTER_S 0
801 #define PFNUM_S 0
804 #define PCIE_FW_A 0x30b8
805 #define PCIE_FW_PF_A 0x30bc
807 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
833 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
887 /* SPARE2 register contains 32-bit value at offset 0x6 in Serial INIT
891 #define PCIE_STATIC_SPARE2_A 0x5bfc
894 #define MC_INT_CAUSE_A 0x7518
895 #define MC_P_INT_CAUSE_A 0x41318
905 #define PERR_INT_CAUSE_S 0
909 #define DBG_GPIO_EN_A 0x6010
910 #define XGMAC_PORT_CFG_A 0x1000
911 #define MAC_PORT_CFG_A 0x800
917 #define MC_ECC_STATUS_A 0x751c
918 #define MC_P_ECC_STATUS_A 0x4131c
921 #define ECC_CECNT_M 0xffffU
925 #define ECC_UECNT_S 0
926 #define ECC_UECNT_M 0xffffU
930 #define MC_BIST_CMD_A 0x7600
939 #define BIST_OPCODE_S 0
942 #define MC_BIST_CMD_ADDR_A 0x7604
943 #define MC_BIST_CMD_LEN_A 0x7608
944 #define MC_BIST_DATA_PATTERN_A 0x760c
946 #define MC_BIST_STATUS_RDATA_A 0x7688
949 #define MA_EDRAM0_BAR_A 0x77c0
952 #define EDRAM0_BASE_M 0xfffU
955 #define EDRAM0_SIZE_S 0
956 #define EDRAM0_SIZE_M 0xfffU
960 #define MA_EDRAM1_BAR_A 0x77c4
963 #define EDRAM1_BASE_M 0xfffU
966 #define EDRAM1_SIZE_S 0
967 #define EDRAM1_SIZE_M 0xfffU
971 #define MA_EXT_MEMORY_BAR_A 0x77c8
974 #define EXT_MEM_BASE_M 0xfffU
978 #define EXT_MEM_SIZE_S 0
979 #define EXT_MEM_SIZE_M 0xfffU
983 #define MA_EXT_MEMORY1_BAR_A 0x7808
990 #define EXT_MEM1_BASE_M 0xfffU
993 #define EXT_MEM1_SIZE_S 0
994 #define EXT_MEM1_SIZE_M 0xfffU
998 #define MA_EXT_MEMORY0_BAR_A 0x77c8
1001 #define EXT_MEM0_BASE_M 0xfffU
1004 #define EXT_MEM0_SIZE_S 0
1005 #define EXT_MEM0_SIZE_M 0xfffU
1009 #define MA_TARGET_MEM_ENABLE_A 0x77d8
1019 #define EDRAM0_ENABLE_S 0
1031 #define MA_INT_CAUSE_A 0x77e0
1037 #define MEM_WRAP_INT_CAUSE_S 0
1041 #define MA_INT_WRAP_STATUS_A 0x77e4
1044 #define MEM_WRAP_ADDRESS_M 0xfffffffU
1047 #define MEM_WRAP_CLIENT_NUM_S 0
1048 #define MEM_WRAP_CLIENT_NUM_M 0xfU
1052 #define MA_PARITY_ERROR_STATUS_A 0x77f4
1053 #define MA_PARITY_ERROR_STATUS1_A 0x77f4
1054 #define MA_PARITY_ERROR_STATUS2_A 0x7804
1057 #define EDC_0_BASE_ADDR 0x7900
1059 #define EDC_BIST_CMD_A 0x7904
1060 #define EDC_BIST_CMD_ADDR_A 0x7908
1061 #define EDC_BIST_CMD_LEN_A 0x790c
1062 #define EDC_BIST_DATA_PATTERN_A 0x7910
1063 #define EDC_BIST_STATUS_RDATA_A 0x7928
1064 #define EDC_INT_CAUSE_A 0x7978
1078 #define EDC_ECC_STATUS_A 0x797c
1081 #define EDC_1_BASE_ADDR 0x7980
1084 #define CIM_BOOT_CFG_A 0x7b00
1085 #define CIM_SDRAM_BASE_ADDR_A 0x7b14
1086 #define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1087 #define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1088 #define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1089 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1091 #define BOOTADDR_M 0xffffff00U
1093 #define UPCRST_S 0
1097 #define CIM_PF_MAILBOX_DATA_A 0x240
1098 #define CIM_PF_MAILBOX_CTRL_A 0x280
1108 #define MBOWNER_S 0
1109 #define MBOWNER_M 0x3U
1113 #define CIM_PF_HOST_INT_ENABLE_A 0x288
1119 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
1125 #define CIM_HOST_INT_CAUSE_A 0x7b2c
1143 #define UPACCNONZERO_S 0
1203 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1325 #define RSVDSPACEINT_S 0
1335 #define DBGLAWPTR_M 0x7fU
1342 #define DBGLARPTR_S 0
1343 #define DBGLARPTR_M 0x7fU
1350 #define TP_DBG_LA_DATAL_A 0x7ed8
1351 #define TP_DBG_LA_CONFIG_A 0x7ed4
1352 #define TP_OUT_CONFIG_A 0x7d04
1353 #define TP_GLOBAL_CONFIG_A 0x7d08
1359 #define TP_CMM_TCB_BASE_A 0x7d10
1360 #define TP_CMM_MM_BASE_A 0x7d14
1361 #define TP_CMM_TIMER_BASE_A 0x7d18
1362 #define TP_PMM_TX_BASE_A 0x7d20
1363 #define TP_PMM_RX_BASE_A 0x7d28
1364 #define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1365 #define TP_PMM_RX_MAX_PAGE_A 0x7d30
1366 #define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1367 #define TP_PMM_TX_MAX_PAGE_A 0x7d38
1368 #define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1375 #define PMTXNUMCHN_M 0x3U
1378 #define PMTXMAXPAGE_S 0
1379 #define PMTXMAXPAGE_M 0x1fffffU
1382 #define PMRXMAXPAGE_S 0
1383 #define PMRXMAXPAGE_M 0x1fffffU
1387 #define DBGLAMODE_M 0x3U
1391 #define FIVETUPLELOOKUP_M 0x3U
1395 #define TP_PARA_REG2_A 0x7d68
1398 #define MAXRXDATA_M 0xffffU
1401 #define TP_TIMER_RESOLUTION_A 0x7d90
1404 #define TIMERRESOLUTION_M 0xffU
1408 #define TIMESTAMPRESOLUTION_M 0xffU
1412 #define DELAYEDACKRESOLUTION_S 0
1413 #define DELAYEDACKRESOLUTION_M 0xffU
1417 #define TP_SHIFT_CNT_A 0x7dc0
1418 #define TP_RXT_MIN_A 0x7d98
1419 #define TP_RXT_MAX_A 0x7d9c
1420 #define TP_PERS_MIN_A 0x7da0
1421 #define TP_PERS_MAX_A 0x7da4
1422 #define TP_KEEP_IDLE_A 0x7da8
1423 #define TP_KEEP_INTVL_A 0x7dac
1424 #define TP_INIT_SRTT_A 0x7db0
1425 #define TP_DACK_TIMER_A 0x7db4
1426 #define TP_FINWAIT2_TIMER_A 0x7db8
1428 #define INITSRTT_S 0
1429 #define INITSRTT_M 0xffffU
1432 #define PERSMAX_S 0
1433 #define PERSMAX_M 0x3fffffffU
1438 #define SYNSHIFTMAX_M 0xffU
1443 #define RXTSHIFTMAXR1_M 0xfU
1448 #define RXTSHIFTMAXR2_M 0xfU
1453 #define PERSHIFTBACKOFFMAX_M 0xfU
1459 #define PERSHIFTMAX_M 0xfU
1464 #define KEEPALIVEMAXR1_M 0xfU
1468 #define KEEPALIVEMAXR2_S 0
1469 #define KEEPALIVEMAXR2_M 0xfU
1476 #define TP_CCTRL_TABLE_A 0x7ddc
1477 #define TP_PACE_TABLE_A 0x7dd8
1478 #define TP_MTU_TABLE_A 0x7de4
1484 #define MTUWIDTH_M 0xfU
1488 #define MTUVALUE_S 0
1489 #define MTUVALUE_M 0x3fffU
1493 #define TP_RSS_LKP_TABLE_A 0x7dec
1494 #define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1495 #define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1496 #define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1503 #define LKPTBLQUEUE1_M 0x3ffU
1506 #define LKPTBLQUEUE0_S 0
1507 #define LKPTBLQUEUE0_M 0x3ffU
1510 #define TP_TM_PIO_ADDR_A 0x7e18
1511 #define TP_TM_PIO_DATA_A 0x7e1c
1512 #define TP_MOD_CONFIG_A 0x7e24
1515 #define TIMERMODE_M 0xffU
1518 #define TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A 0x3
1519 #define TP_TX_MOD_Q1_Q0_RATE_LIMIT_A 0x8
1521 #define TP_PIO_ADDR_A 0x7e40
1522 #define TP_PIO_DATA_A 0x7e44
1523 #define TP_MIB_INDEX_A 0x7e50
1524 #define TP_MIB_DATA_A 0x7e54
1525 #define TP_INT_CAUSE_A 0x7e74
1527 #define TP_FLM_FREE_PS_CNT_A 0x7e80
1528 #define TP_FLM_FREE_RX_CNT_A 0x7e84
1530 #define FREEPSTRUCTCOUNT_S 0
1531 #define FREEPSTRUCTCOUNT_M 0x1fffffU
1534 #define FREERXPAGECOUNT_S 0
1535 #define FREERXPAGECOUNT_M 0x1fffffU
1539 #define TP_FLM_FREE_TX_CNT_A 0x7e88
1541 #define FREETXPAGECOUNT_S 0
1542 #define FREETXPAGECOUNT_M 0x1fffffU
1550 #define TP_TX_ORATE_A 0x7ebc
1553 #define OFDRATE3_M 0xffU
1557 #define OFDRATE2_M 0xffU
1561 #define OFDRATE1_M 0xffU
1564 #define OFDRATE0_S 0
1565 #define OFDRATE0_M 0xffU
1568 #define TP_TX_TRATE_A 0x7ed0
1571 #define TNLRATE3_M 0xffU
1575 #define TNLRATE2_M 0xffU
1579 #define TNLRATE1_M 0xffU
1582 #define TNLRATE0_S 0
1583 #define TNLRATE0_M 0xffU
1586 #define TP_VLAN_PRI_MAP_A 0x140
1624 #define FCOE_S 0
1636 #define TP_INGRESS_CONFIG_A 0x141
1650 #define TP_MIB_MAC_IN_ERR_0_A 0x0
1651 #define TP_MIB_HDR_IN_ERR_0_A 0x4
1652 #define TP_MIB_TCP_IN_ERR_0_A 0x8
1653 #define TP_MIB_TCP_OUT_RST_A 0xc
1654 #define TP_MIB_TCP_IN_SEG_HI_A 0x10
1655 #define TP_MIB_TCP_IN_SEG_LO_A 0x11
1656 #define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1657 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1658 #define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1659 #define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1660 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1661 #define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1662 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1663 #define TP_MIB_TCP_V6OUT_RST_A 0x2c
1664 #define TP_MIB_OFD_ARP_DROP_A 0x36
1665 #define TP_MIB_CPL_IN_REQ_0_A 0x38
1666 #define TP_MIB_CPL_OUT_RSP_0_A 0x3c
1667 #define TP_MIB_TNL_DROP_0_A 0x44
1668 #define TP_MIB_FCOE_DDP_0_A 0x48
1669 #define TP_MIB_FCOE_DROP_0_A 0x4c
1670 #define TP_MIB_FCOE_BYTE_0_HI_A 0x50
1671 #define TP_MIB_OFD_VLN_DROP_0_A 0x58
1672 #define TP_MIB_USM_PKTS_A 0x5c
1673 #define TP_MIB_RQE_DFR_PKT_A 0x64
1675 #define ULP_TX_INT_CAUSE_A 0x8dcc
1676 #define ULP_TX_TPT_LLIMIT_A 0x8dd4
1677 #define ULP_TX_TPT_ULIMIT_A 0x8dd8
1678 #define ULP_TX_PBL_LLIMIT_A 0x8ddc
1679 #define ULP_TX_PBL_ULIMIT_A 0x8de0
1680 #define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1698 #define PM_RX_INT_CAUSE_A 0x8fdc
1699 #define PM_RX_STAT_CONFIG_A 0x8fc8
1700 #define PM_RX_STAT_COUNT_A 0x8fcc
1701 #define PM_RX_STAT_LSB_A 0x8fd0
1702 #define PM_RX_DBG_CTRL_A 0x8fd0
1703 #define PM_RX_DBG_DATA_A 0x8fd4
1704 #define PM_RX_DBG_STAT_MSB_A 0x10013
1706 #define PMRX_FRAMING_ERROR_F 0x003ffff0U
1724 #define ULP_TX_LA_RDPTR_0_A 0x8ec0
1725 #define ULP_TX_LA_RDDATA_0_A 0x8ec4
1726 #define ULP_TX_LA_WRPTR_0_A 0x8ec8
1727 #define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f70
1729 #define ULP_TX_ASIC_DEBUG_0_A 0x8f74
1730 #define ULP_TX_ASIC_DEBUG_1_A 0x8f78
1731 #define ULP_TX_ASIC_DEBUG_2_A 0x8f7c
1732 #define ULP_TX_ASIC_DEBUG_3_A 0x8f80
1733 #define ULP_TX_ASIC_DEBUG_4_A 0x8f84
1736 #define PM_RX_BASE_ADDR 0x8fc0
1738 #define PMRX_E_PCMD_PAR_ERROR_S 0
1742 #define PM_TX_INT_CAUSE_A 0x8ffc
1743 #define PM_TX_STAT_CONFIG_A 0x8fe8
1744 #define PM_TX_STAT_COUNT_A 0x8fec
1745 #define PM_TX_STAT_LSB_A 0x8ff0
1746 #define PM_TX_DBG_CTRL_A 0x8ff0
1747 #define PM_TX_DBG_DATA_A 0x8ff4
1748 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1766 #define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1776 #define PMTX_C_PCMD_PAR_ERROR_S 0
1780 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1781 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1782 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1783 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1784 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1785 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1786 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1787 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1788 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1789 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1790 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1791 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1792 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1793 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1794 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1795 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1796 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1797 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1798 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1799 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1800 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1801 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1802 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1803 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1804 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1805 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1806 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1807 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1808 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1809 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1810 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1811 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1812 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1813 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1814 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1815 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1816 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1817 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1818 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1819 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1820 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1821 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1822 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1823 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1824 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1825 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1826 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1827 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1828 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1829 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1830 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1831 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1832 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1833 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1834 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1835 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1836 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1837 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1838 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1839 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1840 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1841 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1842 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1843 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1844 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1845 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1846 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1847 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1848 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1849 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1850 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1851 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1852 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1853 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1854 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1855 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1856 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1857 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1858 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1859 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1860 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1861 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1862 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1863 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1864 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1865 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1866 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1867 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1868 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1869 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1870 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1871 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1872 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1873 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1874 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1875 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1876 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1877 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1878 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1879 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1880 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1881 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1882 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1883 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1884 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1885 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1886 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1887 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1888 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1889 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1890 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1891 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1892 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1893 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1894 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1895 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1896 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1897 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1898 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1899 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1900 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1901 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1902 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1903 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1904 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1905 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1906 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1907 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1908 #define MAC_PORT_MAGIC_MACID_LO 0x824
1909 #define MAC_PORT_MAGIC_MACID_HI 0x828
1910 #define MAC_PORT_TX_TS_VAL_LO 0x928
1911 #define MAC_PORT_TX_TS_VAL_HI 0x92c
1913 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1914 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1915 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1916 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1917 #define MAC_PORT_EPIO_OP_A 0x8d0
1919 #define MAC_PORT_CFG2_A 0x818
1921 #define MAC_PORT_PTP_SUM_LO_A 0x990
1922 #define MAC_PORT_PTP_SUM_HI_A 0x994
1924 #define MPS_CMN_CTL_A 0x9000
1942 #define NUMPORTS_S 0
1943 #define NUMPORTS_M 0x3U
1946 #define MPS_INT_CAUSE_A 0x9008
1947 #define MPS_TX_INT_CAUSE_A 0x9408
1948 #define MPS_STAT_CTL_A 0x9600
1963 #define TXDESCFIFO_M 0xfU
1967 #define TXDATAFIFO_M 0xfU
1974 #define TPFIFO_S 0
1975 #define TPFIFO_M 0xfU
1978 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1979 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1980 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1982 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1983 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1984 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1985 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1986 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1987 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1988 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1989 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1990 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1991 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1992 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1993 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1994 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1995 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1996 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1997 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1998 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1999 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
2000 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
2001 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
2002 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
2003 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
2004 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
2005 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
2006 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
2007 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
2008 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
2009 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
2010 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
2011 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
2012 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
2013 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
2015 #define MPS_TRC_CFG_A 0x9800
2033 #define TRCMULTIFILTER_S 0
2037 #define MPS_TRC_RSS_CONTROL_A 0x9808
2038 #define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
2039 #define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
2040 #define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
2041 #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
2046 #define QUEUENUMBER_S 0
2058 #define TFPORT_M 0xfU
2063 #define TFLENGTH_M 0x1fU
2067 #define TFOFFSET_S 0
2068 #define TFOFFSET_M 0x1fU
2081 #define T5_TFPORT_M 0x1fU
2085 #define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
2086 #define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
2089 #define TFMINPKTSIZE_M 0x1ffU
2093 #define TFCAPTUREMAX_S 0
2094 #define TFCAPTUREMAX_M 0x3fffU
2098 #define MPS_TRC_FILTER0_MATCH_A 0x9c00
2099 #define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
2100 #define MPS_TRC_FILTER1_MATCH_A 0x9d00
2102 #define TP_RSS_CONFIG_A 0x7df0
2212 #define DISABLE_S 0
2216 #define TP_RSS_CONFIG_TNL_A 0x7df4
2219 #define MASKSIZE_M 0xfU
2224 #define MASKFILTER_M 0x7ffU
2228 #define USEWIRECH_S 0
2240 #define TP_RSS_CONFIG_OFD_A 0x7df8
2247 #define RRCPLQUEWIDTH_M 0xfU
2251 #define TP_RSS_CONFIG_SYN_A 0x7dfc
2252 #define TP_RSS_CONFIG_VRT_A 0x7e00
2279 #define HASHDELAY_M 0xfU
2284 #define VFWRADDR_M 0x7fU
2289 #define KEYMODE_M 0x3U
2301 #define KEYWRADDR_S 0
2302 #define KEYWRADDR_M 0xfU
2307 #define KEYWRADDRX_M 0x3U
2316 #define LKPIDXSIZE_M 0x3U
2320 #define TP_RSS_VFL_CONFIG_A 0x3a
2321 #define TP_RSS_VFH_CONFIG_A 0x3b
2344 #define DEFAULTQUEUE_M 0x3ffU
2359 #define KEYINDEX_S 0
2360 #define KEYINDEX_M 0xfU
2371 #define LE_DB_DBGI_CONFIG_A 0x19cf0
2381 #define DBGICMDMODE_S 0
2382 #define DBGICMDMODE_M 0x3U
2385 #define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
2388 #define DBGICMD_M 0xfU
2391 #define DBGITID_S 0
2392 #define DBGITID_M 0xfffffU
2395 #define LE_DB_DBGI_REQ_DATA_A 0x19d00
2396 #define LE_DB_DBGI_RSP_STATUS_A 0x19d94
2398 #define LE_DB_DBGI_RSP_DATA_A 0x19da0
2425 #define IVFWIDTH_M 0xfU
2430 #define CH1DEFAULTQUEUE_M 0x3ffU
2434 #define CH0DEFAULTQUEUE_S 0
2435 #define CH0DEFAULTQUEUE_M 0x3ffU
2440 #define VFLKPIDX_M 0xffU
2444 #define T6_VFWRADDR_M 0xffU
2448 #define TP_RSS_CONFIG_CNG_A 0x7e04
2449 #define TP_RSS_SECRET_KEY0_A 0x40
2450 #define TP_RSS_PF0_CONFIG_A 0x30
2451 #define TP_RSS_PF_MAP_A 0x38
2452 #define TP_RSS_PF_MSK_A 0x39
2456 #define PF0LKPIDX_M 0x7U
2459 #define PF1MSKSIZE_M 0xfU
2533 #define QUEUE_S 0
2534 #define QUEUE_M 0x3ffU
2538 #define MPS_TRC_INT_CAUSE_A 0x985c
2545 #define PKTFIFO_M 0xfU
2548 #define FILTMEM_S 0
2549 #define FILTMEM_M 0xfU
2552 #define MPS_CLS_INT_CAUSE_A 0xd028
2562 #define MATCHSRAM_S 0
2566 #define MPS_RX_PG_RSV0_A 0x11010
2567 #define MPS_RX_PG_RSV4_A 0x11020
2568 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2569 #define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2570 #define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2572 #define MPS_RX_VXLAN_TYPE_A 0x11234
2578 #define VXLAN_S 0
2579 #define VXLAN_M 0xffffU
2583 #define MPS_RX_GENEVE_TYPE_A 0x11238
2589 #define GENEVE_S 0
2590 #define GENEVE_M 0xffffU
2594 #define MPS_CLS_TCAM_Y_L_A 0xf000
2595 #define MPS_CLS_TCAM_DATA0_A 0xf000
2596 #define MPS_CLS_TCAM_DATA1_A 0xf004
2601 #define MPS_VF_RPLCT_MAP0_A 0x1111c
2602 #define MPS_VF_RPLCT_MAP1_A 0x11120
2603 #define MPS_VF_RPLCT_MAP2_A 0x11124
2604 #define MPS_VF_RPLCT_MAP3_A 0x11128
2605 #define MPS_VF_RPLCT_MAP4_A 0x11300
2606 #define MPS_VF_RPLCT_MAP5_A 0x11304
2607 #define MPS_VF_RPLCT_MAP6_A 0x11308
2608 #define MPS_VF_RPLCT_MAP7_A 0x1130c
2611 #define VIDL_M 0xffffU
2615 #define DATALKPTYPE_M 0x3U
2619 #define DATAPORTNUM_M 0xfU
2624 #define DATALKPTYPE_M 0x3U
2636 #define DATAVIDH1_S 0
2637 #define DATAVIDH1_M 0x7fU
2640 #define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
2641 #define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
2642 #define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
2645 #define USED_M 0x7ffU
2648 #define ALLOC_S 0
2649 #define ALLOC_M 0x7ffU
2653 #define T5_USED_M 0xfffU
2656 #define T5_ALLOC_S 0
2657 #define T5_ALLOC_M 0xfffU
2660 #define DMACH_S 0
2661 #define DMACH_M 0xffffU
2664 #define MPS_CLS_TCAM_X_L_A 0xf008
2665 #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2686 #define MPS_CLS_SRAM_L_A 0xe000
2691 #define T6_SRAM_PRIO3_M 0x7U
2695 #define T6_SRAM_PRIO2_M 0x7U
2699 #define T6_SRAM_PRIO1_M 0x7U
2703 #define T6_SRAM_PRIO0_M 0x7U
2715 #define T6_PF_M 0x7U
2722 #define T6_VF_S 0
2723 #define T6_VF_M 0xffU
2726 #define MPS_CLS_SRAM_H_A 0xe004
2741 #define PF_M 0x7U
2748 #define VF_S 0
2749 #define VF_M 0x7fU
2753 #define SRAM_PRIO3_M 0x7U
2757 #define SRAM_PRIO2_M 0x7U
2761 #define SRAM_PRIO1_M 0x7U
2765 #define SRAM_PRIO0_M 0x7U
2772 #define PORTMAP_S 0
2773 #define PORTMAP_M 0xfU
2776 #define CPL_INTR_CAUSE_A 0x19054
2798 #define ZERO_SWITCH_ERROR_S 0
2802 #define SMB_INT_CAUSE_A 0x19090
2816 #define ULP_RX_INT_CAUSE_A 0x19158
2817 #define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2818 #define ULP_RX_ISCSI_ULIMIT_A 0x19160
2819 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2820 #define ULP_RX_ISCSI_PSZ_A 0x19168
2821 #define ULP_RX_TDDP_LLIMIT_A 0x1916c
2822 #define ULP_RX_TDDP_ULIMIT_A 0x19170
2823 #define ULP_RX_STAG_LLIMIT_A 0x1917c
2824 #define ULP_RX_STAG_ULIMIT_A 0x19180
2825 #define ULP_RX_RQ_LLIMIT_A 0x19184
2826 #define ULP_RX_RQ_ULIMIT_A 0x19188
2827 #define ULP_RX_PBL_LLIMIT_A 0x1918c
2828 #define ULP_RX_PBL_ULIMIT_A 0x19190
2829 #define ULP_RX_CTX_BASE_A 0x19194
2830 #define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2831 #define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2832 #define ULP_RX_LA_CTL_A 0x1923c
2833 #define ULP_RX_LA_RDPTR_A 0x19240
2834 #define ULP_RX_LA_RDDATA_A 0x19244
2835 #define ULP_RX_LA_WRPTR_A 0x19248
2836 #define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac
2837 #define ULP_RX_TLS_KEY_ULIMIT_A 0x192b0
2848 #define HPZ0_S 0
2851 #define ULP_RX_TDDP_PSZ_A 0x19178
2854 #define SF_DATA_A 0x193f8
2855 #define SF_OP_A 0x193fc
2872 #define OP_S 0
2876 #define PL_PF_INT_CAUSE_A 0x3c0
2886 #define PL_PF_INT_ENABLE_A 0x3c4
2887 #define PL_PF_CTL_A 0x3c8
2889 #define PL_WHOAMI_A 0x19400
2892 #define SOURCEPF_M 0x7U
2896 #define T6_SOURCEPF_M 0x7U
2899 #define PL_INT_CAUSE_A 0x1940c
2989 #define CIM_S 0
2997 #define PL_INT_ENABLE_A 0x19410
2998 #define PL_INT_MAP0_A 0x19414
2999 #define PL_RST_A 0x19428
3005 #define PIORSTMODE_S 0
3009 #define PL_PL_INT_CAUSE_A 0x19430
3015 #define PERRVFID_S 0
3019 #define PL_REV_A 0x1943c
3021 #define REV_S 0
3022 #define REV_M 0xfU
3046 #define LE_DB_CONFIG_A 0x19c04
3047 #define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
3048 #define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
3049 #define LE_DB_FILTER_TABLE_INDEX_A 0x19c14
3050 #define LE_DB_SERVER_INDEX_A 0x19c18
3051 #define LE_DB_SRVR_START_INDEX_A 0x19c18
3052 #define LE_DB_CLIP_TABLE_INDEX_A 0x19c1c
3053 #define LE_DB_ACT_CNT_IPV4_A 0x19c20
3054 #define LE_DB_ACT_CNT_IPV6_A 0x19c24
3055 #define LE_DB_HASH_CONFIG_A 0x19c28
3058 #define HASHTIDSIZE_M 0x3fU
3062 #define HASHTBLSIZE_M 0x1ffffU
3065 #define LE_DB_HASH_TID_BASE_A 0x19c30
3066 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
3067 #define LE_DB_INT_CAUSE_A 0x19c3c
3068 #define LE_DB_CLCAM_TID_BASE_A 0x19df4
3069 #define LE_DB_TID_HASHBASE_A 0x19df8
3070 #define T6_LE_DB_HASH_TID_BASE_A 0x19df8
3101 #define BASEADDR_M 0x1fffffffU
3112 #define LE_DB_RSP_CODE_0_A 0x19c74
3114 #define TCAM_ACTV_HIT_S 0
3115 #define TCAM_ACTV_HIT_M 0x1fU
3119 #define LE_DB_RSP_CODE_1_A 0x19c78
3122 #define HASH_ACTV_HIT_M 0x1fU
3126 #define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac
3127 #define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb0
3129 #define NCSI_INT_CAUSE_A 0x1a0d8
3143 #define RXFIFO_PRTY_ERR_S 0
3147 #define XGMAC_PORT_CFG2_A 0x1018
3157 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
3158 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
3160 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
3161 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
3162 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
3163 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
3164 #define XGMAC_PORT_EPIO_OP_A 0x10d0
3170 #define ADDRESS_S 0
3173 #define MAC_PORT_INT_CAUSE_A 0x8dc
3174 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
3176 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
3178 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
3179 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
3181 #define TX_MOD_QUEUE_REQ_MAP_S 0
3193 #define TX_MODQ_WEIGHT0_S 0
3196 #define TP_TX_SCHED_HDR_A 0x23
3197 #define TP_TX_SCHED_FIFO_A 0x24
3198 #define TP_TX_SCHED_PCMD_A 0x25
3203 #define T5_PORT0_BASE 0x30000
3204 #define T5_PORT_STRIDE 0x4000
3208 #define MC_0_BASE_ADDR 0x40000
3209 #define MC_1_BASE_ADDR 0x48000
3213 #define MC_P_BIST_CMD_A 0x41400
3214 #define MC_P_BIST_CMD_ADDR_A 0x41404
3215 #define MC_P_BIST_CMD_LEN_A 0x41408
3216 #define MC_P_BIST_DATA_PATTERN_A 0x4140c
3217 #define MC_P_BIST_STATUS_RDATA_A 0x41488
3219 #define EDC_T50_BASE_ADDR 0x50000
3221 #define EDC_H_BIST_CMD_A 0x50004
3222 #define EDC_H_BIST_CMD_ADDR_A 0x50008
3223 #define EDC_H_BIST_CMD_LEN_A 0x5000c
3224 #define EDC_H_BIST_DATA_PATTERN_A 0x50010
3225 #define EDC_H_BIST_STATUS_RDATA_A 0x50028
3227 #define EDC_H_ECC_ERR_ADDR_A 0x50084
3228 #define EDC_T51_BASE_ADDR 0x50800
3233 #define PL_VF_REV_A 0x4
3234 #define PL_VF_WHOAMI_A 0x0
3235 #define PL_VF_REVISION_A 0x8
3238 #define CIM_HOST_ACC_CTRL_A 0x7b50
3239 #define CIM_HOST_ACC_DATA_A 0x7b54
3240 #define UP_UP_DBG_LA_CFG_A 0x140
3241 #define UP_UP_DBG_LA_DATA_A 0x144
3251 #define CIM_IBQ_DBG_CFG_A 0x7b60
3254 #define IBQDBGADDR_M 0xfffU
3262 #define IBQDBGEN_S 0
3266 #define CIM_OBQ_DBG_CFG_A 0x7b64
3269 #define OBQDBGADDR_M 0xfffU
3277 #define OBQDBGEN_S 0
3281 #define CIM_IBQ_DBG_DATA_A 0x7b68
3282 #define CIM_OBQ_DBG_DATA_A 0x7b6c
3283 #define CIM_DEBUGCFG_A 0x7b70
3284 #define CIM_DEBUGSTS_A 0x7b74
3287 #define POLADBGRDPTR_M 0x1ffU
3291 #define POLADBGWRPTR_M 0x1ffU
3295 #define PILADBGRDPTR_M 0x1ffU
3298 #define PILADBGWRPTR_S 0
3299 #define PILADBGWRPTR_M 0x1ffU
3306 #define CIM_PO_LA_DEBUGDATA_A 0x7b78
3307 #define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3308 #define CIM_PO_LA_MADEBUGDATA_A 0x7b80
3309 #define CIM_PI_LA_MADEBUGDATA_A 0x7b84
3315 #define UPDBGLAEN_S 0
3320 #define UPDBGLARDPTR_M 0xfffU
3324 #define UPDBGLAWRPTR_M 0xfffU
3331 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
3332 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3335 #define CIMQSIZE_M 0x3fU
3339 #define CIMQBASE_M 0x3fU
3342 #define QUEFULLTHRSH_S 0
3343 #define QUEFULLTHRSH_M 0x1ffU
3346 #define UP_IBQ_0_RDADDR_A 0x10
3347 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3348 #define UP_OBQ_0_REALADDR_A 0x104
3349 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3351 #define IBQRDADDR_S 0
3352 #define IBQRDADDR_M 0x1fffU
3355 #define IBQWRADDR_S 0
3356 #define IBQWRADDR_M 0x1fffU
3359 #define QUERDADDR_S 0
3360 #define QUERDADDR_M 0x7fffU
3363 #define QUEREMFLITS_S 0
3364 #define QUEREMFLITS_M 0x7ffU
3368 #define QUEEOPCNT_M 0xfffU
3371 #define QUESOPCNT_S 0
3372 #define QUESOPCNT_M 0xfffU
3383 #define QUENUMSELECT_S 0