156 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_hw_pci_read_cfg4()
830 	unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);  in t4_get_regs_len()
2643 	unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);  in t4_get_regs()
3365 	unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);  in t4_check_fw_version()
3612 		hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));  in t4_fw_matches_chip()
4501 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {  in sge_intr_handler()
4513 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)  in sge_intr_handler()
4718 	enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);  in le_intr_handler()
5080 	u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?  in t4_intr_enable()
5083 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)  in t4_intr_enable()
5112 	pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?  in t4_intr_disable()
5121 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_chip_rss_size()
5479 	if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&  in t4_write_rss_key()
5528 	if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {  in t4_read_rss_vf_config()
6107 	chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);  in compute_mps_bg_map()
6241 	unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);  in t4_get_tp_ch_map()
6379 	if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {  in t4_get_port_stats()
6413 	if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {  in t4_get_port_stats()
6713 	unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);  in t4_sge_decode_idma_state()
7237 	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)  in t4_fl_pkt_align()
8175 				if (CHELSIO_CHIP_VERSION(adap->params.chip) <=  in t4_change_mac()
9470 	if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {  in t4_init_tp_params()