Lines Matching +full:idma +full:- +full:addr
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
263 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
264 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
265 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
266 u64 rx_trunc0; /* buffer-group 0 truncated packets */
267 u64 rx_trunc1; /* buffer-group 1 truncated packets */
268 u64 rx_trunc2; /* buffer-group 2 truncated packets */
269 u64 rx_trunc3; /* buffer-group 3 truncated packets */
374 * places we store their offsets here, or a -1 if the field isn't
407 unsigned int tc; /* PCI-E traffic class */
480 u8 fw_caps_support; /* 32-bit Port Capabilities */
498 unsigned int idma_state[2]; /* IDMA Hang detect state */
499 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
503 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
509 u64 timestamp; /* OS-dependent timestamp */
569 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
570 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
574 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
575 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
599 bool new_module; /* ->OS Transceiver Module inserted */
600 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
733 struct sge_fl { /* SGE free-buffer queue state */
748 dma_addr_t addr; /* bus address of HW ring start */ member
820 unsigned long imm; /* # of immediate-data packets */
840 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ member
844 unsigned int in_use; /* # of in-use Tx descriptors */
1005 void **egr_map; /* qid->queue egress queue map */
1006 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
1013 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */
1014 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
1017 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
1018 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
1024 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
1025 * Configuration initialization for T5 only has SR-IOV functionality enabled
1026 * on PF0-3 in order to simplify everything.
1040 u8 addr[ETH_ALEN]; member
1087 u8 addr[ETH_ALEN]; member
1126 /* MSI-X Info for NIC and OFLD queues */
1134 u8 chan_map[NCHAN]; /* channel -> port map */
1234 /* Ethtool n-tuple */
1238 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1246 u8 mode; /* per-class or per-flow */
1270 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1271 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
1328 * We really need to come up with a hardware-independent mechanism to
1334 * filter match rules -- up to a maximum of 36 bits. Because
1350 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1351 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1377 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1396 * packet -- potentially with some Ethernet header rewriting.
1445 NAT_MODE_ALL /* NAT on entire 4-tuple */
1452 * firmware command. The use of bit-field structure elements is purely to
1470 * internal forms -- for instance the Ingress Queue ID passed in from
1478 return adap->params.offload; in is_offload()
1483 return adap->params.hash_filter; in is_hashfilter()
1488 return adap->params.crypto; in is_pci_uld()
1493 return (adap->params.offload || adap->params.crypto); in is_uld()
1498 return adap->params.ethofld; in is_ethofld()
1503 return readl(adap->regs + reg_addr); in t4_read_reg()
1508 writel(val, adap->regs + reg_addr); in t4_write_reg()
1512 static inline u64 readq(const volatile void __iomem *addr) in readq() argument
1514 return readl(addr) + ((u64)readl(addr + 4) << 32); in readq()
1517 static inline void writeq(u64 val, volatile void __iomem *addr) in writeq() argument
1519 writel(val, addr); in writeq()
1520 writel(val >> 32, addr + 4); in writeq()
1526 return readq(adap->regs + reg_addr); in t4_read_reg64()
1531 writeq(val, adap->regs + reg_addr); in t4_write_reg64()
1535 * t4_set_hw_addr - store a port's MAC address in SW
1546 eth_hw_addr_set(adapter->port[port_idx], hw_addr); in t4_set_hw_addr()
1547 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); in t4_set_hw_addr()
1551 * netdev2pinfo - return the port_info structure associated with a net_device
1562 * adap2pinfo - return the port_info of a port
1570 return netdev_priv(adap->port[idx]); in adap2pinfo()
1574 * netdev2adap - return the adapter structure associated with a net_device
1581 return netdev2pinfo(dev)->adapter; in netdev2adap()
1585 * - bits 0..9: chip version
1586 * - bits 10..15: chip revision
1587 * - bits 16..23: register dump version
1591 return CHELSIO_CHIP_VERSION(ap->params.chip) | in mk_adap_vers()
1592 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); in mk_adap_vers()
1595 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1599 unsigned int idx = q->intr_params >> 1; in qtimer_val()
1601 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; in qtimer_val()
1649 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1653 return adap->params.bypass; in is_bypass()
1683 return adap->params.vpd.cclk / 1000; in core_ticks_per_usec()
1689 return (us * adap->params.vpd.cclk) / 1000; in us_to_core_ticks()
1696 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / in core_ticks_to_us()
1697 adapter->params.vpd.cclk); in core_ticks_to_us()
1703 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); in dack_ticks_to_usec()
1706 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1735 * hash_mac_addr - return the hash value of a MAC address
1736 * @addr: the 48-bit Ethernet MAC address
1741 static inline int hash_mac_addr(const u8 *addr) in hash_mac_addr() argument
1743 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; in hash_mac_addr()
1744 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; in hash_mac_addr()
1758 q->adap = adap; in init_rspq()
1760 q->iqe_len = iqe_size; in init_rspq()
1761 q->size = size; in init_rspq()
1765 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1823 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1824 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1828 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1830 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, in t4_memory_write() argument
1833 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); in t4_memory_write()
1844 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1920 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1922 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1938 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2000 const u8 *addr, const u8 *mask, unsigned int idx,
2005 const u8 *addr, const u8 *mask, unsigned int vni,
2009 const u8 *addr, const u8 *mask, unsigned int idx,
2013 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
2016 const u8 **addr, bool sleep_ok);
2018 int idx, const u8 *addr, bool persist, u8 *smt_idx);
2061 u32 addr, u32 val);
2075 struct sge_idma_monitor_state *idma);
2077 struct sge_idma_monitor_state *idma,
2080 unsigned int naddr, u8 *addr);
2112 dma_addr_t *addr);
2117 const dma_addr_t *addr);
2120 const dma_addr_t *addr, u32 start, u32 send_len);
2133 int *tcam_idx, const u8 *addr,
2138 const u8 **addr, u16 *idx,
2141 unsigned int naddr, const u8 **addr, bool sleep_ok);
2145 const u8 *addr, const u8 *mask,
2152 const u8 *addr,
2160 const u8 *addr,
2167 int *tcam_idx, const u8 *addr,