Lines Matching +full:0 +full:x744
2 #define A_SG_CONTROL 0x0
25 #define M_USERSPACESIZE 0x1f
29 #define M_HOSTPAGESIZE 0x7
37 #define M_PKTSHIFT 0x7
52 #define S_GLOBALENABLE 0
68 #define A_SG_KDOORBELL 0x4
74 #define S_EGRCNTX 0
75 #define M_EGRCNTX 0xffff
78 #define A_SG_GTS 0x8
81 #define M_RSPQ 0x7
86 #define M_NEWTIMER 0x1fff
89 #define S_NEWINDEX 0
90 #define M_NEWINDEX 0xffff
93 #define A_SG_CONTEXT_CMD 0xc
96 #define M_CONTEXT_CMD_OPCODE 0xf
105 #define M_CQ_CREDIT 0x7f
128 #define S_CONTEXT 0
129 #define M_CONTEXT 0xffff
134 #define A_SG_CONTEXT_DATA0 0x10
136 #define A_SG_CONTEXT_DATA1 0x14
138 #define A_SG_CONTEXT_DATA2 0x18
140 #define A_SG_CONTEXT_DATA3 0x1c
142 #define A_SG_CONTEXT_MASK0 0x20
144 #define A_SG_CONTEXT_MASK1 0x24
146 #define A_SG_CONTEXT_MASK2 0x28
148 #define A_SG_CONTEXT_MASK3 0x2c
150 #define A_SG_RSPQ_CREDIT_RETURN 0x30
152 #define S_CREDITS 0
153 #define M_CREDITS 0xffff
156 #define A_SG_DATA_INTR 0x34
162 #define A_SG_HI_DRB_HI_THRSH 0x38
164 #define A_SG_HI_DRB_LO_THRSH 0x3c
166 #define A_SG_LO_DRB_HI_THRSH 0x40
168 #define A_SG_LO_DRB_LO_THRSH 0x44
170 #define A_SG_RSPQ_FL_STATUS 0x4c
178 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
181 #define M_HIRCQDRBTHRSH 0x7ff
184 #define S_LORCQDRBTHRSH 0
185 #define M_LORCQDRBTHRSH 0x7ff
188 #define A_SG_EGR_CNTX_BADDR 0x58
190 #define A_SG_INT_CAUSE 0x5c
209 #define M_FLPARITYERROR 0x3f
214 #define M_ITPARITYERROR 0x3
286 #define A_SG_INT_ENABLE 0x60
288 #define A_SG_CMDQ_CREDIT_TH 0x64
291 #define M_TIMEOUT 0xffffff
294 #define S_THRESHOLD 0
295 #define M_THRESHOLD 0xff
298 #define A_SG_TIMER_TICK 0x68
300 #define A_SG_CQ_CONTEXT_BADDR 0x6c
302 #define A_SG_OCO_BASE 0x70
305 #define M_BASE1 0xffff
308 #define A_SG_DRB_PRI_THRESH 0x74
310 #define A_PCIX_INT_ENABLE 0x80
313 #define M_MSIXPARERR 0x7
318 #define M_CFPARERR 0xf
323 #define M_RFPARERR 0xf
328 #define M_WFPARERR 0x3
376 #define S_MSTDETPARERR 0
380 #define A_PCIX_INT_CAUSE 0x84
382 #define A_PCIX_CFG 0x88
392 #define A_PCIX_MODE 0x8c
395 #define M_PCLKRANGE 0x3
400 #define M_PCIXINITPAT 0xf
404 #define S_64BIT 0
408 #define A_PCIE_INT_ENABLE 0x80
411 #define M_BISTERR 0xff
432 #define M_PCIE_MSIXPARERR 0x7
460 #define S_PEXERR 0
464 #define A_PCIE_INT_CAUSE 0x84
470 #define A_PCIE_CFG 0x88
484 #define S_CRSTWRMMODE 0
488 #define A_PCIE_MODE 0x8c
491 #define M_NUMFSTTRNSEQRX 0xff
495 #define A_PCIE_PEX_CTRL0 0x98
498 #define M_NUMFSTTRNSEQ 0xff
503 #define M_REPLAYLMT 0xfffff
507 #define A_PCIE_PEX_CTRL1 0x9c
509 #define S_T3A_ACKLAT 0
510 #define M_T3A_ACKLAT 0x7ff
514 #define S_ACKLAT 0
515 #define M_ACKLAT 0x1fff
519 #define A_PCIE_PEX_ERR 0xa4
521 #define A_T3DBG_GPIO_EN 0xd0
587 #define S_GPIO0_OUT_VAL 0
591 #define A_T3DBG_INT_ENABLE 0xd8
633 #define S_GPIO0 0
637 #define A_T3DBG_INT_CAUSE 0xdc
639 #define A_T3DBG_GPIO_ACT_LOW 0xf0
641 #define MC7_PMRX_BASE_ADDR 0x100
643 #define A_MC7_CFG 0x100
658 #define M_WIDTH 0x3
671 #define M_DEN 0x7
679 #define S_CLKEN 0
683 #define A_MC7_MODE 0x104
689 #define A_MC7_EXT_MODE1 0x108
691 #define A_MC7_EXT_MODE2 0x10c
693 #define A_MC7_EXT_MODE3 0x110
695 #define A_MC7_PRE 0x114
697 #define A_MC7_REF 0x118
700 #define M_PREREFDIV 0x3fff
703 #define S_PERREFEN 0
707 #define A_MC7_DLL 0x11c
713 #define S_DLLRST 0
717 #define A_MC7_PARM 0x120
720 #define M_ACTTOPREDLY 0xf
724 #define M_ACTTORDWRDLY 0x7
728 #define M_PRECYC 0x7
732 #define M_REFCYC 0x7f
736 #define M_BKCYC 0x1f
740 #define M_WRTORDDLY 0xf
743 #define S_RDTOWRDLY 0
744 #define M_RDTOWRDLY 0xf
747 #define A_MC7_CAL 0x128
757 #define A_MC7_ERR_ADDR 0x12c
759 #define A_MC7_ECC 0x130
765 #define S_ECCGENEN 0
769 #define A_MC7_CE_ADDR 0x134
771 #define A_MC7_CE_DATA0 0x138
773 #define A_MC7_CE_DATA1 0x13c
775 #define A_MC7_CE_DATA2 0x140
777 #define S_DATA 0
778 #define M_DATA 0xff
782 #define A_MC7_UE_ADDR 0x144
784 #define A_MC7_UE_DATA0 0x148
786 #define A_MC7_UE_DATA1 0x14c
788 #define A_MC7_UE_DATA2 0x150
790 #define A_MC7_BD_ADDR 0x154
794 #define M_ADDR 0x1fffffff
796 #define A_MC7_BD_DATA0 0x158
798 #define A_MC7_BD_DATA1 0x15c
800 #define A_MC7_BD_OP 0x164
802 #define S_OP 0
807 #define A_MC7_BIST_ADDR_BEG 0x168
809 #define A_MC7_BIST_ADDR_END 0x16c
811 #define A_MC7_BIST_DATA 0x170
813 #define A_MC7_BIST_OP 0x174
819 #define A_MC7_INT_ENABLE 0x178
826 #define M_PE 0x7fff
836 #define S_CE 0
840 #define A_MC7_INT_CAUSE 0x17c
842 #define MC7_PMTX_BASE_ADDR 0x180
844 #define MC7_CM_BASE_ADDR 0x200
846 #define A_CIM_BOOT_CFG 0x280
849 #define M_BOOTADDR 0x3fffffff
852 #define A_CIM_SDRAM_BASE_ADDR 0x28c
854 #define A_CIM_SDRAM_ADDR_SIZE 0x290
856 #define A_CIM_HOST_INT_ENABLE 0x298
906 #define A_CIM_HOST_INT_CAUSE 0x29c
952 #define S_RSVDSPACEINT 0
956 #define A_CIM_HOST_ACC_CTRL 0x2b0
962 #define A_CIM_HOST_ACC_DATA 0x2b4
964 #define A_CIM_IBQ_DBG_CFG 0x2c0
967 #define M_IBQDBGADDR 0x1ff
972 #define M_IBQDBGQID 0x3
984 #define S_IBQDBGEN 0
988 #define A_CIM_IBQ_DBG_DATA 0x2c8
990 #define A_TP_IN_CONFIG 0x300
1008 #define A_TP_OUT_CONFIG 0x304
1012 #define A_TP_GLOBAL_CONFIG 0x308
1034 #define S_IPTTL 0
1035 #define M_IPTTL 0xff
1038 #define A_TP_CMM_MM_BASE 0x314
1040 #define A_TP_CMM_TIMER_BASE 0x318
1043 #define M_CMTIMERMAXNUM 0x3
1046 #define A_TP_PMM_SIZE 0x31c
1048 #define A_TP_PMM_TX_BASE 0x320
1050 #define A_TP_PMM_RX_BASE 0x328
1052 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
1054 #define A_TP_PMM_RX_MAX_PAGE 0x330
1056 #define A_TP_PMM_TX_PAGE_SIZE 0x334
1058 #define A_TP_PMM_TX_MAX_PAGE 0x338
1060 #define A_TP_TCP_OPTIONS 0x340
1063 #define M_MTUDEFAULT 0xffff
1076 #define M_SACKMODE 0x3
1081 #define M_WINDOWSCALEMODE 0x3
1084 #define S_TIMESTAMPSMODE 0
1086 #define M_TIMESTAMPSMODE 0x3
1090 #define A_TP_DACK_CONFIG 0x344
1093 #define M_AUTOSTATE3 0x3
1097 #define M_AUTOSTATE2 0x3
1101 #define M_AUTOSTATE1 0x3
1105 #define M_BYTETHRESHOLD 0xfffff
1109 #define M_MSSTHRESHOLD 0x3
1120 #define S_DACK_MODE 0
1124 #define A_TP_PC_CONFIG 0x348
1162 #define S_TABLELATENCYDELTA 0
1163 #define M_TABLELATENCYDELTA 0xf
1168 #define A_TP_PC_CONFIG2 0x34c
1190 #define A_TP_TCP_BACKOFF_REG0 0x350
1192 #define A_TP_TCP_BACKOFF_REG1 0x354
1194 #define A_TP_TCP_BACKOFF_REG2 0x358
1196 #define A_TP_TCP_BACKOFF_REG3 0x35c
1198 #define A_TP_PARA_REG2 0x368
1201 #define M_MAXRXDATA 0xffff
1204 #define S_RXCOALESCESIZE 0
1205 #define M_RXCOALESCESIZE 0xffff
1208 #define A_TP_PARA_REG3 0x36c
1211 #define M_TXDATAACKIDX 0xf
1231 #define S_RXCOALESCEPSHEN 0
1235 #define A_TP_PARA_REG4 0x370
1237 #define A_TP_PARA_REG5 0x374
1243 #define A_TP_PARA_REG6 0x378
1253 #define A_TP_PARA_REG7 0x37c
1256 #define M_PMMAXXFERLEN1 0xffff
1259 #define S_PMMAXXFERLEN0 0
1260 #define M_PMMAXXFERLEN0 0xffff
1263 #define A_TP_TIMER_RESOLUTION 0x390
1266 #define M_TIMERRESOLUTION 0xff
1270 #define M_TIMESTAMPRESOLUTION 0xff
1273 #define S_DELAYEDACKRESOLUTION 0
1274 #define M_DELAYEDACKRESOLUTION 0xff
1277 #define A_TP_MSL 0x394
1279 #define A_TP_RXT_MIN 0x398
1281 #define A_TP_RXT_MAX 0x39c
1283 #define A_TP_PERS_MIN 0x3a0
1285 #define A_TP_PERS_MAX 0x3a4
1287 #define A_TP_KEEP_IDLE 0x3a8
1289 #define A_TP_KEEP_INTVL 0x3ac
1291 #define A_TP_INIT_SRTT 0x3b0
1293 #define A_TP_DACK_TIMER 0x3b4
1295 #define A_TP_FINWAIT2_TIMER 0x3b8
1297 #define A_TP_SHIFT_CNT 0x3c0
1301 #define M_SYNSHIFTMAX 0xff
1307 #define M_RXTSHIFTMAXR1 0xf
1313 #define M_RXTSHIFTMAXR2 0xf
1318 #define M_PERSHIFTBACKOFFMAX 0xf
1322 #define M_PERSHIFTMAX 0xf
1325 #define S_KEEPALIVEMAX 0
1327 #define M_KEEPALIVEMAX 0xff
1331 #define A_TP_MTU_PORT_TABLE 0x3d0
1333 #define A_TP_CCTRL_TABLE 0x3dc
1335 #define A_TP_MTU_TABLE 0x3e4
1337 #define A_TP_RSS_MAP_TABLE 0x3e8
1339 #define A_TP_RSS_LKP_TABLE 0x3ec
1341 #define A_TP_RSS_CONFIG 0x3f0
1368 #define M_RRCPLCPUSIZE 0x7
1379 #define S_DISABLE 0
1381 #define A_TP_TM_PIO_ADDR 0x418
1383 #define A_TP_TM_PIO_DATA 0x41c
1385 #define A_TP_TX_MOD_QUE_TABLE 0x420
1387 #define A_TP_TX_RESOURCE_LIMIT 0x424
1389 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1391 #define S_TX_MOD_QUEUE_REQ_MAP 0
1392 #define M_TX_MOD_QUEUE_REQ_MAP 0xff
1395 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1397 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1399 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
1401 #define A_TP_MOD_RATE_LIMIT 0x438
1403 #define A_TP_PIO_ADDR 0x440
1405 #define A_TP_PIO_DATA 0x444
1407 #define A_TP_RESET 0x44c
1413 #define S_TPRESET 0
1417 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
1419 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
1421 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
1423 #define A_TP_MIB_INDEX 0x450
1425 #define A_TP_MIB_RDATA 0x454
1427 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1429 #define A_TP_INT_ENABLE 0x470
1447 #define A_TP_INT_CAUSE 0x474
1449 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1451 #define A_TP_TX_DROP_CFG_CH0 0x12b
1453 #define A_TP_TX_DROP_MODE 0x12f
1455 #define A_TP_EGRESS_CONFIG 0x145
1457 #define S_REWRITEFORCETOSIZE 0
1461 #define A_TP_TX_TRC_KEY0 0x20
1463 #define A_TP_RX_TRC_KEY0 0x120
1465 #define A_TP_TX_DROP_CNT_CH0 0x12d
1467 #define S_TXDROPCNTCH0RCVD 0
1468 #define M_TXDROPCNTCH0RCVD 0xffff
1473 #define A_TP_PROXY_FLOW_CNTL 0x4b0
1475 #define A_TP_EMBED_OP_FIELD0 0x4e8
1476 #define A_TP_EMBED_OP_FIELD1 0x4ec
1477 #define A_TP_EMBED_OP_FIELD2 0x4f0
1478 #define A_TP_EMBED_OP_FIELD3 0x4f4
1479 #define A_TP_EMBED_OP_FIELD4 0x4f8
1480 #define A_TP_EMBED_OP_FIELD5 0x4fc
1482 #define A_ULPRX_CTL 0x500
1488 #define A_ULPRX_INT_ENABLE 0x504
1518 #define S_PARERRDATA 0
1522 #define A_ULPRX_INT_CAUSE 0x508
1524 #define A_ULPRX_ISCSI_LLIMIT 0x50c
1526 #define A_ULPRX_ISCSI_ULIMIT 0x510
1528 #define A_ULPRX_ISCSI_TAGMASK 0x514
1530 #define A_ULPRX_ISCSI_PSZ 0x518
1532 #define A_ULPRX_TDDP_LLIMIT 0x51c
1534 #define A_ULPRX_TDDP_ULIMIT 0x520
1535 #define A_ULPRX_TDDP_PSZ 0x528
1537 #define S_HPZ0 0
1538 #define M_HPZ0 0xf
1542 #define A_ULPRX_STAG_LLIMIT 0x52c
1544 #define A_ULPRX_STAG_ULIMIT 0x530
1546 #define A_ULPRX_RQ_LLIMIT 0x534
1548 #define A_ULPRX_RQ_ULIMIT 0x538
1550 #define A_ULPRX_PBL_LLIMIT 0x53c
1552 #define A_ULPRX_PBL_ULIMIT 0x540
1554 #define A_ULPRX_TDDP_TAGMASK 0x524
1556 #define A_ULPTX_CONFIG 0x580
1562 #define S_CFG_RR_ARB 0
1566 #define A_ULPTX_INT_ENABLE 0x584
1572 #define S_PBL_BOUND_ERR_CH0 0
1576 #define A_ULPTX_INT_CAUSE 0x588
1578 #define A_ULPTX_TPT_LLIMIT 0x58c
1580 #define A_ULPTX_TPT_ULIMIT 0x590
1582 #define A_ULPTX_PBL_LLIMIT 0x594
1584 #define A_ULPTX_PBL_ULIMIT 0x598
1586 #define A_ULPTX_DMA_WEIGHT 0x5ac
1589 #define M_D1_WEIGHT 0xffff
1592 #define S_D0_WEIGHT 0
1593 #define M_D0_WEIGHT 0xffff
1596 #define A_PM1_RX_CFG 0x5c0
1597 #define A_PM1_RX_MODE 0x5c4
1599 #define A_PM1_RX_INT_ENABLE 0x5d8
1654 #define M_IESPI_PAR_ERROR 0x7
1658 #define S_OCSPI_PAR_ERROR 0
1659 #define M_OCSPI_PAR_ERROR 0x7
1663 #define A_PM1_RX_INT_CAUSE 0x5dc
1665 #define A_PM1_TX_CFG 0x5e0
1666 #define A_PM1_TX_MODE 0x5e4
1668 #define A_PM1_TX_INT_ENABLE 0x5f8
1723 #define M_ICSPI_PAR_ERROR 0x7
1727 #define S_OESPI_PAR_ERROR 0
1728 #define M_OESPI_PAR_ERROR 0x7
1732 #define A_PM1_TX_INT_CAUSE 0x5fc
1734 #define A_MPS_CFG 0x600
1752 #define S_PORT0ACTIVE 0
1760 #define A_MPS_INT_ENABLE 0x61c
1763 #define M_MCAPARERRENB 0x7
1768 #define M_RXTPPARERRENB 0x3
1773 #define M_TX1TPPARERRENB 0x3
1777 #define S_TX0TPPARERRENB 0
1778 #define M_TX0TPPARERRENB 0x3
1782 #define A_MPS_INT_CAUSE 0x620
1785 #define M_MCAPARERR 0x7
1790 #define M_RXTPPARERR 0x3
1795 #define M_TX1TPPARERR 0x3
1799 #define S_TX0TPPARERR 0
1800 #define M_TX0TPPARERR 0x3
1804 #define A_CPL_SWITCH_CNTRL 0x640
1806 #define A_CPL_INTR_ENABLE 0x650
1828 #define S_ZERO_SWITCH_ERROR 0
1832 #define A_CPL_INTR_CAUSE 0x654
1834 #define A_CPL_MAP_TBL_DATA 0x65c
1836 #define A_SMB_GLOBAL_TIME_CFG 0x660
1838 #define A_I2C_CFG 0x6a0
1840 #define S_I2C_CLKDIV 0
1841 #define M_I2C_CLKDIV 0xfff
1844 #define A_MI1_CFG 0x6b0
1847 #define M_CLKDIV 0xff
1852 #define M_ST 0x3
1866 #define S_MDIEN 0
1870 #define A_MI1_ADDR 0x6b4
1873 #define M_PHYADDR 0x1f
1876 #define S_REGADDR 0
1877 #define M_REGADDR 0x1f
1880 #define A_MI1_DATA 0x6b8
1882 #define A_MI1_OP 0x6bc
1884 #define S_MDI_OP 0
1885 #define M_MDI_OP 0x3
1888 #define A_SF_DATA 0x6d8
1890 #define A_SF_OP 0x6dc
1893 #define M_BYTECNT 0x3
1896 #define A_PL_INT_ENABLE0 0x6e0
1962 #define S_SGE3 0
1966 #define A_PL_INT_CAUSE0 0x6e4
1968 #define A_PL_RST 0x6f0
1978 #define A_PL_REV 0x6f4
1980 #define A_PL_CLI 0x6f8
1982 #define A_MC5_DB_CONFIG 0x704
1989 #define M_TMPARTSIZE 0x3
1994 #define M_TMTYPE 0x3
2022 #define S_TMMODE 0
2026 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
2028 #define A_MC5_DB_FILTER_TABLE 0x710
2030 #define A_MC5_DB_SERVER_INDEX 0x714
2032 #define A_MC5_DB_RSP_LATENCY 0x720
2035 #define M_RDLAT 0x1f
2039 #define M_LRNLAT 0x1f
2042 #define S_SRCHLAT 0
2043 #define M_SRCHLAT 0x1f
2046 #define A_MC5_DB_PART_ID_INDEX 0x72c
2048 #define A_MC5_DB_INT_ENABLE 0x740
2078 #define A_MC5_DB_INT_CAUSE 0x744
2080 #define A_MC5_DB_DBGI_CONFIG 0x774
2082 #define A_MC5_DB_DBGI_REQ_CMD 0x778
2084 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
2086 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
2088 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
2090 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
2092 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
2094 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
2096 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
2098 #define S_DBGIRSPVALID 0
2102 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
2104 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
2106 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
2108 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
2110 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
2112 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
2114 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
2116 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
2118 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
2120 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
2122 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
2124 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
2126 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
2128 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
2130 #define A_MC5_DB_DATA_READ_CMD 0x7f8
2132 #define XGMAC0_0_BASE_ADDR 0x800
2134 #define A_XGM_TX_CTRL 0x800
2136 #define S_TXEN 0
2140 #define A_XGM_TX_CFG 0x804
2142 #define S_TXPAUSEEN 0
2146 #define A_XGM_TX_PAUSE_QUANTA 0x808
2148 #define A_XGM_RX_CTRL 0x80c
2150 #define S_RXEN 0
2154 #define A_XGM_RX_CFG 0x810
2176 #define S_COPYALLFRAMES 0
2184 #define A_XGM_RX_HASH_LOW 0x814
2186 #define A_XGM_RX_HASH_HIGH 0x818
2188 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
2190 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
2192 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
2194 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
2196 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
2198 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
2200 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
2202 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
2204 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
2206 #define A_XGM_INT_STATUS 0x86c
2212 #define A_XGM_XGM_INT_ENABLE 0x874
2213 #define A_XGM_XGM_INT_DISABLE 0x878
2215 #define A_XGM_STAT_CTRL 0x880
2221 #define A_XGM_RXFIFO_CFG 0x884
2228 #define M_RXFIFOPAUSEHWM 0xfff
2235 #define M_RXFIFOPAUSELWM 0xfff
2245 #define S_DISERRFRAMES 0
2249 #define A_XGM_TXFIFO_CFG 0x888
2256 #define M_TXIPG 0xff
2261 #define M_TXFIFOTHRESH 0x1ff
2269 #define A_XGM_SERDES_CTRL 0x890
2270 #define A_XGM_SERDES_CTRL0 0x8e0
2284 #define A_XGM_PAUSE_TIMER 0x890
2286 #define A_XGM_RGMII_IMP 0x89c
2293 #define M_RGMIIIMPPD 0x7
2296 #define S_RGMIIIMPPU 0
2297 #define M_RGMIIIMPPU 0x7
2308 #define A_XGM_XAUI_IMP 0x8a0
2319 #define M_CALIMP 0x1f
2323 #define S_XAUIIMP 0
2324 #define M_XAUIIMP 0x7
2327 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
2330 #define M_RXMAXFRAMERSIZE 0x3fff
2338 #define S_RXMAXPKTSIZE 0
2339 #define M_RXMAXPKTSIZE 0x3fff
2343 #define A_XGM_RESET_CTRL 0x8ac
2361 #define S_MAC_RESET_ 0
2365 #define A_XGM_PORT_CFG 0x8b8
2372 #define M_PORTSPEED 0x3
2376 #define S_ENRGMII 0
2380 #define A_XGM_INT_ENABLE 0x8d4
2383 #define M_TXFIFO_PRTY_ERR 0x7
2388 #define M_RXFIFO_PRTY_ERR 0x7
2401 #define M_SERDES_LOS 0xf
2413 #define S_XGM_INT 0
2417 #define A_XGM_INT_CAUSE 0x8d8
2419 #define A_XGM_XAUI_ACT_CTRL 0x8dc
2465 #define A_XGM_SERDES_STAT0 0x8f0
2466 #define A_XGM_SERDES_STAT1 0x8f4
2467 #define A_XGM_SERDES_STAT2 0x8f8
2469 #define S_LOWSIG0 0
2473 #define A_XGM_SERDES_STAT3 0x8fc
2475 #define A_XGM_STAT_TX_BYTE_LOW 0x900
2477 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
2479 #define A_XGM_STAT_TX_FRAME_LOW 0x908
2481 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2483 #define A_XGM_STAT_TX_BCAST 0x910
2485 #define A_XGM_STAT_TX_MCAST 0x914
2487 #define A_XGM_STAT_TX_PAUSE 0x918
2489 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
2491 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2493 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2495 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2497 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2499 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2501 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2503 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
2505 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
2507 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
2509 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
2511 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2513 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2515 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2517 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2519 #define A_XGM_STAT_RX_64B_FRAMES 0x958
2521 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2523 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2525 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2527 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2529 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2531 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2533 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2535 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2537 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2539 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2541 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2543 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2545 #define A_XGM_SERDES_STATUS0 0x98c
2547 #define A_XGM_SERDES_STATUS1 0x990
2553 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2555 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2558 #define M_TXSPI4SOPCNT 0xffff
2562 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2564 #define XGMAC0_1_BASE_ADDR 0xa00