Lines Matching refs:MDIO_MMD_PMAPMD
118 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL, in ael_i2c_rd()
125 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat); in ael_i2c_rd()
129 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA, in ael_i2c_rd()
145 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable); in ael1002_power_down()
148 MDIO_MMD_PMAPMD, MDIO_CTRL1, in ael1002_power_down()
158 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) || in ael1002_reset()
159 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) || in ael1002_reset()
160 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) || in ael1002_reset()
161 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) || in ael1002_reset()
162 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN, in ael1002_reset()
181 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, in get_link_status_r()
224 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait); in ael1006_reset()
296 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 }, in ael2005_setup_sr_edc()
297 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a }, in ael2005_setup_sr_edc()
298 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 }, in ael2005_setup_sr_edc()
317 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, in ael2005_setup_sr_edc()
328 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 }, in ael2005_setup_twinax_edc()
332 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 }, in ael2005_setup_twinax_edc()
333 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 }, in ael2005_setup_twinax_edc()
353 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, in ael2005_setup_twinax_edc()
366 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat); in ael2005_get_module_type()
378 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200); in ael2005_intr_enable()
384 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100); in ael2005_intr_disable()
390 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00); in ael2005_intr_clear()
397 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 }, in ael2005_reset()
398 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 }, in ael2005_reset()
399 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 }, in ael2005_reset()
400 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, in ael2005_reset()
401 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 }, in ael2005_reset()
402 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, in ael2005_reset()
403 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 }, in ael2005_reset()
407 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 }, in ael2005_reset()
408 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 }, in ael2005_reset()
415 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, in ael2005_reset()
420 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0); in ael2005_reset()
459 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat); in ael2005_intr_handler()
464 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, in ael2005_intr_handler()
516 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0, in t3_ael2005_phy_prep()
527 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a }, in ael2020_setup_sr_edc()
530 { MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 }, in ael2020_setup_sr_edc()
531 { MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 }, in ael2020_setup_sr_edc()
532 { MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 }, in ael2020_setup_sr_edc()
555 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 }, in ael2020_setup_twinax_edc()
556 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 }, in ael2020_setup_twinax_edc()
562 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 }, in ael2020_setup_twinax_edc()
568 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 }, in ael2020_setup_twinax_edc()
569 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 }, in ael2020_setup_twinax_edc()
591 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, in ael2020_setup_twinax_edc()
609 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat); in ael2020_get_module_type()
629 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT, in ael2020_intr_enable()
631 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, in ael2020_intr_enable()
635 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, in ael2020_intr_enable()
669 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, in ael2020_intr_disable()
673 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL, in ael2020_intr_disable()
700 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat); in ael2020_intr_clear()
706 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
709 { MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
712 { MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
713 { MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
714 { MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
728 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, in ael2020_reset()
733 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125); in ael2020_reset()
770 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat); in ael2020_intr_handler()
834 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, in get_link_status_x()
879 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) && in t3_qt2045_phy_prep()