36 	AEL100X_TX_CONFIG1 = 0xc002,
37 	AEL1002_PWR_DOWN_HI = 0xc011,
38 	AEL1002_PWR_DOWN_LO = 0xc012,
39 	AEL1002_XFI_EQL = 0xc015,
40 	AEL1002_LB_EN = 0xc017,
41 	AEL_OPT_SETTINGS = 0xc017,
42 	AEL_I2C_CTRL = 0xc30a,
43 	AEL_I2C_DATA = 0xc30b,
44 	AEL_I2C_STAT = 0xc30c,
45 	AEL2005_GPIO_CTRL = 0xc214,
46 	AEL2005_GPIO_STAT = 0xc215,
48 	AEL2020_GPIO_INTR   = 0xc103,	/* Latch High (LH) */
49 	AEL2020_GPIO_CTRL   = 0xc108,	/* Store Clear (SC) */
50 	AEL2020_GPIO_STAT   = 0xc10c,	/* Read Only (RO) */
51 	AEL2020_GPIO_CFG    = 0xc110,	/* Read Write (RW) */
53 	AEL2020_GPIO_SDA    = 0,	/* IN: i2c serial data */
64 	MODULE_DEV_ADDR	= 0xa0,
65 	SFF_DEV_ADDR	= 0xa2,
70 	phy_transtype_unknown = 0,
88 	for (err = 0; rv->mmd_addr && !err; rv++) {  in set_phy_regs()
89 		if (rv->clear_bits == 0xffff)  in set_phy_regs()
103 		phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;  in ael100x_txon()
106 	t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);  in ael100x_txon()
123 	for (i = 0; i < 200; i++) {  in ael_i2c_rd()
157 	if ((err = ael1002_power_down(phy, 0)) ||  in ael1002_reset()
159 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||  in ael1002_reset()
160 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||  in ael1002_reset()
161 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||  in ael1002_reset()
163 				       0, 1 << 5)))  in ael1002_reset()
165 	return 0;  in ael1002_reset()
170 	return 0;  in ael1002_intr_noop()
198 	return 0;  in get_link_status_r()
219 	return 0;  in t3_ael1002_phy_prep()
245 	return 0;  in t3_ael1006_phy_prep()
260 	if (v < 0)  in ael2xxx_get_module_type()
263 	if (v == 0x10)  in ael2xxx_get_module_type()
265 	if (v == 0x20)  in ael2xxx_get_module_type()
267 	if (v == 0x40)  in ael2xxx_get_module_type()
271 	if (v < 0)  in ael2xxx_get_module_type()
277 	if (v < 0)  in ael2xxx_get_module_type()
280 	if (v & 0x80) {  in ael2xxx_get_module_type()
281 		v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);  in ael2xxx_get_module_type()
282 		if (v < 0)  in ael2xxx_get_module_type()
296 		{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },  in ael2005_setup_sr_edc()
297 		{ MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },  in ael2005_setup_sr_edc()
298 		{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },  in ael2005_setup_sr_edc()
299 		{ 0, 0, 0, 0 }  in ael2005_setup_sr_edc()
316 	for (i = 0; i <  EDC_OPT_AEL2005_SIZE / sizeof(u16) && !err; i += 2)  in ael2005_setup_sr_edc()
328 		{ MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },  in ael2005_setup_twinax_edc()
329 		{ 0, 0, 0, 0 }  in ael2005_setup_twinax_edc()
332 		{ MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },  in ael2005_setup_twinax_edc()
333 		{ MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },  in ael2005_setup_twinax_edc()
334 		{ 0, 0, 0, 0 }  in ael2005_setup_twinax_edc()
352 	for (i = 0; i <  EDC_TWX_AEL2005_SIZE / sizeof(u16) && !err; i += 2)  in ael2005_setup_twinax_edc()
378 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);  in ael2005_intr_enable()
384 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);  in ael2005_intr_disable()
390 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);  in ael2005_intr_clear()
397 		{ MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },  in ael2005_reset()
398 		{ MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },  in ael2005_reset()
399 		{ MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },  in ael2005_reset()
400 		{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },  in ael2005_reset()
401 		{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },  in ael2005_reset()
402 		{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },  in ael2005_reset()
403 		{ MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },  in ael2005_reset()
404 		{ 0, 0, 0, 0 }  in ael2005_reset()
407 		{ MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },  in ael2005_reset()
408 		{ MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },  in ael2005_reset()
409 		{ 0, 0, 0, 0 }  in ael2005_reset()
420 	err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);  in ael2005_reset()
432 	err = ael2005_get_module_type(phy, 0);  in ael2005_reset()
433 	if (err < 0)  in ael2005_reset()
457 	int ret, edc_needed, cause = 0;  in ael2005_intr_handler()
465 				    0xd00);  in ael2005_intr_handler()
471 		if (ret < 0)  in ael2005_intr_handler()
484 			ret = ael2005_reset(phy, 0);  in ael2005_intr_handler()
491 	if (ret < 0)  in ael2005_intr_handler()
516 	return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,  in t3_ael2005_phy_prep()
527 		{ MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },  in ael2020_setup_sr_edc()
530 		{ MDIO_MMD_PMAPMD, 0xcb1b, 0xffff, 0x0200 },  in ael2020_setup_sr_edc()
531 		{ MDIO_MMD_PMAPMD, 0xcb1c, 0xffff, 0x00f0 },  in ael2020_setup_sr_edc()
532 		{ MDIO_MMD_PMAPMD, 0xcc06, 0xffff, 0x00e0 },  in ael2020_setup_sr_edc()
535 		{ 0, 0, 0, 0 }  in ael2020_setup_sr_edc()
545 	return 0;  in ael2020_setup_sr_edc()
555 		{ MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },  in ael2020_setup_twinax_edc()
556 		{ MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },  in ael2020_setup_twinax_edc()
557 		{ 0, 0, 0, 0 }  in ael2020_setup_twinax_edc()
562 		{ MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },  in ael2020_setup_twinax_edc()
563 		{ 0, 0, 0, 0 }  in ael2020_setup_twinax_edc()
568 		{ MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },  in ael2020_setup_twinax_edc()
569 		{ MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },  in ael2020_setup_twinax_edc()
570 		{ 0, 0, 0, 0 }  in ael2020_setup_twinax_edc()
590 	for (i = 0; i <  EDC_TWX_AEL2020_SIZE / sizeof(u16) && !err; i += 2)  in ael2020_setup_twinax_edc()
613 	if (stat & (0x1 << (AEL2020_GPIO_MODDET*4))) {  in ael2020_get_module_type()
630 			0xffff, 0x4 },  in ael2020_intr_enable()
632 			0xffff, 0x8 << (AEL2020_GPIO_LSTAT*4) },  in ael2020_intr_enable()
636 			0xffff, 0x2 << (AEL2020_GPIO_MODDET*4) },  in ael2020_intr_enable()
639 		{ 0, 0, 0, 0 }  in ael2020_intr_enable()
641 	int err, link_ok = 0;  in ael2020_intr_enable()
659 	return 0;  in ael2020_intr_enable()
670 			0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },  in ael2020_intr_disable()
674 			0xffff, 0x1 << (AEL2020_GPIO_MODDET*4) },  in ael2020_intr_disable()
677 		{ 0, 0, 0, 0 }  in ael2020_intr_disable()
706 	{ MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
709 	{ MDIO_MMD_PMAPMD, 0xcd40, 0xffff, 0x0001 },
712 	{ MDIO_MMD_PMAPMD, 0xff02, 0xffff, 0x0023 },
713 	{ MDIO_MMD_PMAPMD, 0xff03, 0xffff, 0x0000 },
714 	{ MDIO_MMD_PMAPMD, 0xff04, 0xffff, 0x0000 },
717 	{ 0, 0, 0, 0 }
745 	err = ael2020_get_module_type(phy, 0);  in ael2020_reset()
746 	if (err < 0)  in ael2020_reset()
768 	int ret, edc_needed, cause = 0;  in ael2020_intr_handler()
774 	if (stat & (0x1 << AEL2020_GPIO_MODDET)) {  in ael2020_intr_handler()
777 		if (ret < 0)  in ael2020_intr_handler()
790 			ret = ael2020_reset(phy, 0);  in ael2020_intr_handler()
797 	if (ret < 0)  in ael2020_intr_handler()
851 	return 0;  in get_link_status_x()
875 	 * Some cards where the PHY is supposed to be at address 0 actually  in t3_qt2045_phy_prep()
880 	    stat == 0xffff)  in t3_qt2045_phy_prep()
882 	return 0;  in t3_qt2045_phy_prep()
887 	return 0;  in xaui_direct_reset()
911 	return 0;  in xaui_direct_get_link_status()
916 	return 0;  in xaui_direct_power_down()
935 	return 0;  in t3_xaui_direct_phy_prep()