15 /* The egress WM value 0x01a01fff should be used only when the
18  * enabled, the WM value should be set to 0x014a03F0.
20 #define WM_DISABLE	0x01a01fff
21 #define WM_ENABLE	0x014a03F0
33 #define INITBLOCK_SLEEP	0xffffffff
42 	i = 0;  in vsc_read()
48 	} while (((status & 1) == 0) && (i < 50));  in vsc_read()
57 	/* pr_err("rd: block: 0x%x  sublock: 0x%x  reg: 0x%x  data: 0x%x\n",  in vsc_read()
58 		((addr&0xe000)>>13), ((addr&0x1e00)>>9),  in vsc_read()
59 		((addr&0x01fe)>>1), *val); */  in vsc_read()
66 	t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);  in vsc_write()
67 	t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);  in vsc_write()
68 	/* pr_err("wr: block: 0x%x  sublock: 0x%x  reg: 0x%x  data: 0x%x\n",  in vsc_write()
69 		((addr&0xe000)>>13), ((addr&0x1e00)>>9),  in vsc_write()
70 		((addr&0x01fe)>>1), data); */  in vsc_write()
78 	u32 result = 0xffff;  in vsc7326_full_reset()
84 	val |= 0x1;	/* Enable mac MAC itself */  in vsc7326_full_reset()
85 	val |= 0x800;	/* Turn off the red LED */  in vsc7326_full_reset()
88 	vsc_write(adapter, REG_SW_RESET, 0x80000001);  in vsc7326_full_reset()
92 	} while (result != 0x0);  in vsc7326_full_reset()
96 	{      REG_IFACE_MODE, 0x00000000 },
97 	{         REG_CRC_CFG, 0x00000020 },
98 	{   REG_PLL_CLK_SPEED, 0x00050c00 },
99 	{   REG_PLL_CLK_SPEED, 0x00050c00 },
100 	{            REG_MSCH, 0x00002f14 },
101 	{       REG_SPI4_MISC, 0x00040409 },
102 	{     REG_SPI4_DESKEW, 0x00080000 },
103 	{ REG_SPI4_ING_SETUP2, 0x08080004 },
104 	{ REG_SPI4_ING_SETUP0, 0x04111004 },
105 	{ REG_SPI4_EGR_SETUP0, 0x80001a04 },
106 	{ REG_SPI4_ING_SETUP1, 0x02010000 },
107 	{      REG_AGE_INC(0), 0x00000000 },
108 	{      REG_AGE_INC(1), 0x00000000 },
109 	{     REG_ING_CONTROL, 0x0a200011 },
110 	{     REG_EGR_CONTROL, 0xa0010091 },
114 	{	/* Port 0 */
116 		{           REG_DBG(0), 0x000004f0 },
117 		{           REG_HDX(0), 0x00073101 },
118 		{        REG_TEST(0,0), 0x00000022 },
119 		{        REG_TEST(1,0), 0x00000022 },
120 		{  REG_TOP_BOTTOM(0,0), 0x003f0000 },
121 		{  REG_TOP_BOTTOM(1,0), 0x00120000 },
122 		{ REG_HIGH_LOW_WM(0,0), 0x07460757 },
123 		{ REG_HIGH_LOW_WM(1,0), WM_DISABLE },
124 		{   REG_CT_THRHLD(0,0), 0x00000000 },
125 		{   REG_CT_THRHLD(1,0), 0x00000000 },
126 		{         REG_BUCKE(0), 0x0002ffff },
127 		{         REG_BUCKI(0), 0x0002ffff },
128 		{        REG_TEST(0,0), 0x00000020 },
129 		{        REG_TEST(1,0), 0x00000020 },
131 		{       REG_MAX_LEN(0), 0x00002710 },
132 		{     REG_PORT_FAIL(0), 0x00000002 },
133 		{    REG_NORMALIZER(0), 0x00000a64 },
134 		{        REG_DENORM(0), 0x00000010 },
135 		{     REG_STICK_BIT(0), 0x03baa370 },
136 		{     REG_DEV_SETUP(0), 0x00000083 },
137 		{     REG_DEV_SETUP(0), 0x00000082 },
138 		{      REG_MODE_CFG(0), 0x0200259f },
142 		{           REG_DBG(1), 0x000004f0 },
143 		{           REG_HDX(1), 0x00073101 },
144 		{        REG_TEST(0,1), 0x00000022 },
145 		{        REG_TEST(1,1), 0x00000022 },
146 		{  REG_TOP_BOTTOM(0,1), 0x007e003f },
147 		{  REG_TOP_BOTTOM(1,1), 0x00240012 },
148 		{ REG_HIGH_LOW_WM(0,1), 0x07460757 },
150 		{   REG_CT_THRHLD(0,1), 0x00000000 },
151 		{   REG_CT_THRHLD(1,1), 0x00000000 },
152 		{         REG_BUCKE(1), 0x0002ffff },
153 		{         REG_BUCKI(1), 0x0002ffff },
154 		{        REG_TEST(0,1), 0x00000020 },
155 		{        REG_TEST(1,1), 0x00000020 },
157 		{       REG_MAX_LEN(1), 0x00002710 },
158 		{     REG_PORT_FAIL(1), 0x00000002 },
159 		{    REG_NORMALIZER(1), 0x00000a64 },
160 		{        REG_DENORM(1), 0x00000010 },
161 		{     REG_STICK_BIT(1), 0x03baa370 },
162 		{     REG_DEV_SETUP(1), 0x00000083 },
163 		{     REG_DEV_SETUP(1), 0x00000082 },
164 		{      REG_MODE_CFG(1), 0x0200259f },
168 		{           REG_DBG(2), 0x000004f0 },
169 		{           REG_HDX(2), 0x00073101 },
170 		{        REG_TEST(0,2), 0x00000022 },
171 		{        REG_TEST(1,2), 0x00000022 },
172 		{  REG_TOP_BOTTOM(0,2), 0x00bd007e },
173 		{  REG_TOP_BOTTOM(1,2), 0x00360024 },
174 		{ REG_HIGH_LOW_WM(0,2), 0x07460757 },
176 		{   REG_CT_THRHLD(0,2), 0x00000000 },
177 		{   REG_CT_THRHLD(1,2), 0x00000000 },
178 		{         REG_BUCKE(2), 0x0002ffff },
179 		{         REG_BUCKI(2), 0x0002ffff },
180 		{        REG_TEST(0,2), 0x00000020 },
181 		{        REG_TEST(1,2), 0x00000020 },
183 		{       REG_MAX_LEN(2), 0x00002710 },
184 		{     REG_PORT_FAIL(2), 0x00000002 },
185 		{    REG_NORMALIZER(2), 0x00000a64 },
186 		{        REG_DENORM(2), 0x00000010 },
187 		{     REG_STICK_BIT(2), 0x03baa370 },
188 		{     REG_DEV_SETUP(2), 0x00000083 },
189 		{     REG_DEV_SETUP(2), 0x00000082 },
190 		{      REG_MODE_CFG(2), 0x0200259f },
194 		{           REG_DBG(3), 0x000004f0 },
195 		{           REG_HDX(3), 0x00073101 },
196 		{        REG_TEST(0,3), 0x00000022 },
197 		{        REG_TEST(1,3), 0x00000022 },
198 		{  REG_TOP_BOTTOM(0,3), 0x00fc00bd },
199 		{  REG_TOP_BOTTOM(1,3), 0x00480036 },
200 		{ REG_HIGH_LOW_WM(0,3), 0x07460757 },
202 		{   REG_CT_THRHLD(0,3), 0x00000000 },
203 		{   REG_CT_THRHLD(1,3), 0x00000000 },
204 		{         REG_BUCKE(3), 0x0002ffff },
205 		{         REG_BUCKI(3), 0x0002ffff },
206 		{        REG_TEST(0,3), 0x00000020 },
207 		{        REG_TEST(1,3), 0x00000020 },
209 		{       REG_MAX_LEN(3), 0x00002710 },
210 		{     REG_PORT_FAIL(3), 0x00000002 },
211 		{    REG_NORMALIZER(3), 0x00000a64 },
212 		{        REG_DENORM(3), 0x00000010 },
213 		{     REG_STICK_BIT(3), 0x03baa370 },
214 		{     REG_DEV_SETUP(3), 0x00000083 },
215 		{     REG_DEV_SETUP(3), 0x00000082 },
216 		{      REG_MODE_CFG(3), 0x0200259f },
224 	for (i = 0; i < len; i++) {  in run_table()
235 	int data = 0;  in bist_rd()
236 	u32 result = 0;  in bist_rd()
238 	if ((address != 0x0) &&  in bist_rd()
239 	    (address != 0x1) &&  in bist_rd()
240 	    (address != 0x2) &&  in bist_rd()
241 	    (address != 0xd) &&  in bist_rd()
242 	    (address != 0xe))  in bist_rd()
243 			pr_err("No bist address: 0x%x\n", address);  in bist_rd()
245 	data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |  in bist_rd()
246 		((moduleid & 0xff) << 0));  in bist_rd()
252 	if ((result & (1 << 9)) != 0x0)  in bist_rd()
253 		pr_err("Still in bist read: 0x%x\n", result);  in bist_rd()
254 	else if ((result & (1 << 8)) != 0x0)  in bist_rd()
255 		pr_err("bist read error: 0x%x\n", result);  in bist_rd()
257 	return result & 0xff;  in bist_rd()
262 	int data = 0;  in bist_wr()
263 	u32 result = 0;  in bist_wr()
265 	if ((address != 0x0) &&  in bist_wr()
266 	    (address != 0x1) &&  in bist_wr()
267 	    (address != 0x2) &&  in bist_wr()
268 	    (address != 0xd) &&  in bist_wr()
269 	    (address != 0xe))  in bist_wr()
270 			pr_err("No bist address: 0x%x\n", address);  in bist_wr()
273 		pr_err("Suspicious write out of range value: 0x%x\n", value);  in bist_wr()
275 	data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |  in bist_wr()
276 		((moduleid & 0xff) << 0));  in bist_wr()
282 	if ((result & (1 << 27)) != 0x0)  in bist_wr()
283 		pr_err("Still in bist write: 0x%x\n", result);  in bist_wr()
284 	else if ((result & (1 << 26)) != 0x0)  in bist_wr()
285 		pr_err("bist write error: 0x%x\n", result);  in bist_wr()
287 	return 0;  in bist_wr()
293 	(void) bist_wr(adapter,moduleid, 0x00, 0x02);  in run_bist()
294 	(void) bist_wr(adapter,moduleid, 0x01, 0x01);  in run_bist()
296 	return 0;  in run_bist()
301 	int result=0;  in check_bist()
302 	int column=0;  in check_bist()
304 	result = bist_rd(adapter,moduleid, 0x02);  in check_bist()
305 	column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +  in check_bist()
306 			(bist_rd(adapter,moduleid, 0x0d)));  in check_bist()
307 	if ((result & 3) != 0x3)  in check_bist()
308 		pr_err("Result: 0x%x  BIST error in ram %d, column: 0x%04x\n",  in check_bist()
310 	return 0;  in check_bist()
316 	(void) bist_wr(adapter,moduleid, 0x00, 0x00);  in enable_mem()
317 	return 0;  in enable_mem()
322 	int port = 0;  in run_bist_all()
323 	u32 val = 0;  in run_bist_all()
325 	vsc_write(adapter, REG_MEM_BIST, 0x5);  in run_bist_all()
328 	for (port = 0; port < 12; port++)  in run_bist_all()
329 		vsc_write(adapter, REG_DEV_SETUP(port), 0x0);  in run_bist_all()
332 	vsc_write(adapter, REG_SPI4_MISC, 0x00040409);  in run_bist_all()
350 	vsc_write(adapter, REG_SPI4_MISC, 0x60040400);  in run_bist_all()
352 	for (port = 0; port < 12; port++)  in run_bist_all()
353 		vsc_write(adapter, REG_DEV_SETUP(port), 0x1);  in run_bist_all()
356 	vsc_write(adapter, REG_MEM_BIST, 0x0);  in run_bist_all()
358 	return 0;  in run_bist_all()
363 	return 0;  in mac_intr_handler()
368 	return 0;  in mac_intr_enable()
373 	return 0;  in mac_intr_disable()
378 	return 0;  in mac_intr_clear()
390 		  (addr[0] << 16) | (addr[1] << 8) | addr[2]);  in mac_set_address()
393 	val &= ~0xf0000000;  in mac_set_address()
397 		  0xffff0000 | (addr[4] << 8) | addr[5]);  in mac_set_address()
399 		  0xffff0000 | (addr[2] << 8) | addr[3]);  in mac_set_address()
401 		  0xffff0000 | (addr[0] << 8) | addr[1]);  in mac_set_address()
402 	return 0;  in mac_set_address()
413 	addr[0] = (u8) (addr_hi >> 16);  in mac_get_address()
419 	return 0;  in mac_get_address()
430 	return 0;  in mac_reset()
447 	return 0;  in mac_set_rx_mode()
456 	return 0;  in mac_set_mtu()
465 	if (speed >= 0 && speed != SPEED_10 && speed != SPEED_100 &&  in mac_set_speed_duplex_fc()
468 	if (duplex > 0 && duplex != DUPLEX_FULL)  in mac_set_speed_duplex_fc()
471 	if (speed >= 0) {  in mac_set_speed_duplex_fc()
474 		v &= ~0xf;  in mac_set_speed_duplex_fc()
482 			v = 0x82;  in mac_set_speed_duplex_fc()
484 			v = 0x84;  in mac_set_speed_duplex_fc()
486 			v = 0x86;  in mac_set_speed_duplex_fc()
490 		v &= ~0xff00;  in mac_set_speed_duplex_fc()
492 			v |= 0x400;  in mac_set_speed_duplex_fc()
494 			v |= 0x2000;  in mac_set_speed_duplex_fc()
496 			v |= 0xff00;  in mac_set_speed_duplex_fc()
500 			  speed == SPEED_1000 ? 5 : 0x11);  in mac_set_speed_duplex_fc()
502 			enable = 0x0;	/* 100 or 10 */  in mac_set_speed_duplex_fc()
504 			enable = 0xc;  in mac_set_speed_duplex_fc()
506 			enable = 0x4;  in mac_set_speed_duplex_fc()
507 		enable |= 0x9 << 10;	/* IFG1 */  in mac_set_speed_duplex_fc()
508 		enable |= 0x6 << 6;	/* IFG2 */  in mac_set_speed_duplex_fc()
509 		enable |= 0x1 << 4;	/* VLAN */  in mac_set_speed_duplex_fc()
510 		enable |= 0x3;		/* RX/TX EN */  in mac_set_speed_duplex_fc()
516 	v &= 0xfff0ffff;  in mac_set_speed_duplex_fc()
517 	v |= 0x20000;      /* xon/xoff */  in mac_set_speed_duplex_fc()
519 		v |= 0x40000;  in mac_set_speed_duplex_fc()
521 		v |= 0x80000;  in mac_set_speed_duplex_fc()
523 		v |= 0x10000;  in mac_set_speed_duplex_fc()
525 	return 0;  in mac_set_speed_duplex_fc()
538 		val |= 0x2;  in mac_enable()
542 	return 0;  in mac_enable()
555 		val &= ~0x2;  in mac_disable()
557 		val &= ~0x1;  in mac_disable()
562 	for (i = 0; i <= 0x3a; ++i)  in mac_disable()
563 		vsc_write(mac->adapter, CRA(4, port, i), 0);  in mac_disable()
566 	memset(&mac->stats, 0, sizeof(struct cmac_statistics));  in mac_disable()
568 	return 0;  in mac_disable()
579 	if (v == 0)  in rmon_update()
622 	for (i = 0; i < ARRAY_SIZE(hw_stats); i++)  in port_stats_update()
623 		rmon_update(mac, CRA(0x4, port, p->reg), stats + p->offset);  in port_stats_update()
645 		mac->instance->ticks = 0;  in mac_update_statistics()
697 	mac->instance->ticks = 0;  in vsc7326_mac_create()
699 	i = 0;  in vsc7326_mac_create()
703 		vhi = vlo = 0;  in vsc7326_mac_create()
709 	} while ((++i < 10000) && (val == 0xffffffff));  in vsc7326_mac_create()
719 	return 0;  in vsc7326_mac_reset()