52 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,  in t1_wait_op_done()  argument
56 		u32 val = readl(adapter->regs + reg) & mask;  in t1_wait_op_done()
72 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in __t1_tpi_write()  argument
76 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_write()
77 	writel(value, adapter->regs + A_TPI_WR_DATA);  in __t1_tpi_write()
78 	writel(F_TPIWR, adapter->regs + A_TPI_CSR);  in __t1_tpi_write()
80 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_write()
84 			 adapter->name, addr);  in __t1_tpi_write()
88 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in t1_tpi_write()  argument
92 	spin_lock(&adapter->tpi_lock);  in t1_tpi_write()
93 	ret = __t1_tpi_write(adapter, addr, value);  in t1_tpi_write()
94 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_write()
101 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in __t1_tpi_read()  argument
105 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_read()
106 	writel(0, adapter->regs + A_TPI_CSR);  in __t1_tpi_read()
108 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_read()
112 			 adapter->name, addr);  in __t1_tpi_read()
114 		*valp = readl(adapter->regs + A_TPI_RD_DATA);  in __t1_tpi_read()
118 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in t1_tpi_read()  argument
122 	spin_lock(&adapter->tpi_lock);  in t1_tpi_read()
123 	ret = __t1_tpi_read(adapter, addr, valp);  in t1_tpi_read()
124 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_read()
131 static void t1_tpi_par(adapter_t *adapter, u32 value)  in t1_tpi_par()  argument
133 	writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);  in t1_tpi_par()
141 void t1_link_changed(adapter_t *adapter, int port_id)  in t1_link_changed()  argument
144 	struct cphy *phy = adapter->port[port_id].phy;  in t1_link_changed()
145 	struct link_config *lc = &adapter->port[port_id].link_config;  in t1_link_changed()
156 		struct cmac *mac = adapter->port[port_id].mac;  in t1_link_changed()
161 	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);  in t1_link_changed()
164 static bool t1_pci_intr_handler(adapter_t *adapter)  in t1_pci_intr_handler()  argument
168 	pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);  in t1_pci_intr_handler()
171 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,  in t1_pci_intr_handler()
174 		t1_interrupts_disable(adapter);  in t1_pci_intr_handler()
175 		adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;  in t1_pci_intr_handler()
176 		pr_alert("%s: PCI error encountered.\n", adapter->name);  in t1_pci_intr_handler()
188 static int fpga_phy_intr_handler(adapter_t *adapter)  in fpga_phy_intr_handler()  argument
191 	u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
193 	for_each_port(adapter, p)  in fpga_phy_intr_handler()
195 			struct cphy *phy = adapter->port[p].phy;  in fpga_phy_intr_handler()
199 				t1_link_changed(adapter, p);  in fpga_phy_intr_handler()
201 	writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
208 static irqreturn_t fpga_slow_intr(adapter_t *adapter)  in fpga_slow_intr()  argument
210 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
215 		if (t1_sge_intr_error_handler(adapter->sge))  in fpga_slow_intr()
220 		fpga_phy_intr_handler(adapter);  in fpga_slow_intr()
227 		u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
230 		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
233 		if (t1_pci_intr_handler(adapter))  in fpga_slow_intr()
239 		writel(cause, adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
251 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)  in mi1_wait_until_ready()  argument
258 		__t1_tpi_read(adapter, mi1_reg, &val);  in mi1_wait_until_ready()
264 		pr_alert("%s: MDIO operation timed out\n", adapter->name);  in mi1_wait_until_ready()
271 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)  in mi1_mdio_init()  argument
279 	t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);  in mi1_mdio_init()
289 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_read()  local
293 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_read()
294 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_read()
295 	__t1_tpi_write(adapter,  in mi1_mdio_read()
297 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_read()
298 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_read()
299 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_read()
306 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_write()  local
309 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_write()
310 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_write()
311 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_write()
312 	__t1_tpi_write(adapter,  in mi1_mdio_write()
314 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_write()
315 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_write()
331 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_read()  local
335 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
338 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_read()
339 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_read()
340 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_read()
342 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
345 	__t1_tpi_write(adapter,  in mi1_mdio_ext_read()
347 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
350 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_ext_read()
351 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
358 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_write()  local
361 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
364 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_write()
365 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_write()
366 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_write()
368 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
371 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_ext_write()
372 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);  in mi1_mdio_ext_write()
373 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
374 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
565 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)  in t1_seeprom_read()  argument
574 	pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);  in t1_seeprom_read()
577 		pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);  in t1_seeprom_read()
582 		       adapter->name, addr);  in t1_seeprom_read()
585 	pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);  in t1_seeprom_read()
590 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)  in t1_eeprom_vpd_get()  argument
595 		ret = t1_seeprom_read(adapter, addr,  in t1_eeprom_vpd_get()
604 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])  in vpd_macaddress_get()  argument
608 	if (t1_eeprom_vpd_get(adapter, &vpd))  in vpd_macaddress_get()
634 				   (mac->adapter->params.nports < 2)))  in t1_link_start()
670 int t1_elmer0_ext_intr_handler(adapter_t *adapter)  in t1_elmer0_ext_intr_handler()  argument
676 	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);  in t1_elmer0_ext_intr_handler()
678 	switch (board_info(adapter)->board) {  in t1_elmer0_ext_intr_handler()
685 		for_each_port(adapter, i) {  in t1_elmer0_ext_intr_handler()
690 			phy = adapter->port[i].phy;  in t1_elmer0_ext_intr_handler()
693 				t1_link_changed(adapter, i);  in t1_elmer0_ext_intr_handler()
699 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
702 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
713 		for_each_port(adapter, p) {  in t1_elmer0_ext_intr_handler()
714 			phy = adapter->port[p].phy;  in t1_elmer0_ext_intr_handler()
717 			    t1_link_changed(adapter, p);  in t1_elmer0_ext_intr_handler()
726 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
729 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
734 		if (netif_msg_intr(adapter))  in t1_elmer0_ext_intr_handler()
735 			dev_dbg(&adapter->pdev->dev,  in t1_elmer0_ext_intr_handler()
738 			struct cmac *mac = adapter->port[0].mac;  in t1_elmer0_ext_intr_handler()
745 			t1_tpi_read(adapter,  in t1_elmer0_ext_intr_handler()
747 			if (netif_msg_link(adapter))  in t1_elmer0_ext_intr_handler()
748 				dev_info(&adapter->pdev->dev, "XPAK %s\n",  in t1_elmer0_ext_intr_handler()
753 	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);  in t1_elmer0_ext_intr_handler()
758 void t1_interrupts_enable(adapter_t *adapter)  in t1_interrupts_enable()  argument
762 	adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;  in t1_interrupts_enable()
764 	t1_sge_intr_enable(adapter->sge);  in t1_interrupts_enable()
765 	t1_tp_intr_enable(adapter->tp);  in t1_interrupts_enable()
766 	if (adapter->espi) {  in t1_interrupts_enable()
767 		adapter->slow_intr_mask |= F_PL_INTR_ESPI;  in t1_interrupts_enable()
768 		t1_espi_intr_enable(adapter->espi);  in t1_interrupts_enable()
772 	for_each_port(adapter, i) {  in t1_interrupts_enable()
773 		adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);  in t1_interrupts_enable()
774 		adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);  in t1_interrupts_enable()
778 	if (t1_is_asic(adapter)) {  in t1_interrupts_enable()
779 		u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
782 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,  in t1_interrupts_enable()
785 		adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;  in t1_interrupts_enable()
787 		writel(pl_intr, adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
792 void t1_interrupts_disable(adapter_t* adapter)  in t1_interrupts_disable()  argument
796 	t1_sge_intr_disable(adapter->sge);  in t1_interrupts_disable()
797 	t1_tp_intr_disable(adapter->tp);  in t1_interrupts_disable()
798 	if (adapter->espi)  in t1_interrupts_disable()
799 		t1_espi_intr_disable(adapter->espi);  in t1_interrupts_disable()
802 	for_each_port(adapter, i) {  in t1_interrupts_disable()
803 		adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);  in t1_interrupts_disable()
804 		adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);  in t1_interrupts_disable()
808 	if (t1_is_asic(adapter))  in t1_interrupts_disable()
809 		writel(0, adapter->regs + A_PL_ENABLE);  in t1_interrupts_disable()
812 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);  in t1_interrupts_disable()
814 	adapter->slow_intr_mask = 0;  in t1_interrupts_disable()
818 void t1_interrupts_clear(adapter_t* adapter)  in t1_interrupts_clear()  argument
822 	t1_sge_intr_clear(adapter->sge);  in t1_interrupts_clear()
823 	t1_tp_intr_clear(adapter->tp);  in t1_interrupts_clear()
824 	if (adapter->espi)  in t1_interrupts_clear()
825 		t1_espi_intr_clear(adapter->espi);  in t1_interrupts_clear()
828 	for_each_port(adapter, i) {  in t1_interrupts_clear()
829 		adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);  in t1_interrupts_clear()
830 		adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);  in t1_interrupts_clear()
834 	if (t1_is_asic(adapter)) {  in t1_interrupts_clear()
835 		u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
838 		       adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
842 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);  in t1_interrupts_clear()
848 static irqreturn_t asic_slow_intr(adapter_t *adapter)  in asic_slow_intr()  argument
850 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
853 	cause &= adapter->slow_intr_mask;  in asic_slow_intr()
857 		if (t1_sge_intr_error_handler(adapter->sge))  in asic_slow_intr()
861 		t1_tp_intr_handler(adapter->tp);  in asic_slow_intr()
863 		t1_espi_intr_handler(adapter->espi);  in asic_slow_intr()
865 		if (t1_pci_intr_handler(adapter))  in asic_slow_intr()
873 		adapter->pending_thread_intr |= F_PL_INTR_EXT;  in asic_slow_intr()
874 		adapter->slow_intr_mask &= ~F_PL_INTR_EXT;  in asic_slow_intr()
875 		writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,  in asic_slow_intr()
876 		       adapter->regs + A_PL_ENABLE);  in asic_slow_intr()
881 	writel(cause, adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
882 	readl(adapter->regs + A_PL_CAUSE); /* flush writes */  in asic_slow_intr()
886 irqreturn_t t1_slow_intr_handler(adapter_t *adapter)  in t1_slow_intr_handler()  argument
889 	if (!t1_is_asic(adapter))  in t1_slow_intr_handler()
890 		return fpga_slow_intr(adapter);  in t1_slow_intr_handler()
892 	return asic_slow_intr(adapter);  in t1_slow_intr_handler()
896 static void power_sequence_xpak(adapter_t* adapter)  in power_sequence_xpak()  argument
902 	t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);  in power_sequence_xpak()
905 		t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);  in power_sequence_xpak()
907 		t1_tpi_write(adapter, A_ELMER0_GPO, gpo);  in power_sequence_xpak()
911 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,  in t1_get_board_rev()  argument
919 		u32 val = readl(adapter->regs + A_TP_PC_CONFIG);  in t1_get_board_rev()
937 static int board_init(adapter_t *adapter, const struct board_info *bi)  in board_init()  argument
944 		t1_tpi_par(adapter, 0xf);  in board_init()
945 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);  in board_init()
948 		t1_tpi_par(adapter, 0xf);  in board_init()
949 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);  in board_init()
954 		power_sequence_xpak(adapter);  in board_init()
962 		t1_tpi_par(adapter, 0xf);  in board_init()
963 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);  in board_init()
967 		t1_tpi_par(adapter, 0xf);  in board_init()
968 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);  in board_init()
979 int t1_init_hw_modules(adapter_t *adapter)  in t1_init_hw_modules()  argument
982 	const struct board_info *bi = board_info(adapter);  in t1_init_hw_modules()
985 		u32 val = readl(adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
987 		writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
989 		       adapter->regs + A_MC5_CONFIG);  in t1_init_hw_modules()
992 	if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,  in t1_init_hw_modules()
996 	if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))  in t1_init_hw_modules()
999 	err = t1_sge_configure(adapter->sge, &adapter->params.sge);  in t1_init_hw_modules()
1011 static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)  in get_pci_mode()  argument
1016 	pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);  in get_pci_mode()
1025 void t1_free_sw_modules(adapter_t *adapter)  in t1_free_sw_modules()  argument
1029 	for_each_port(adapter, i) {  in t1_free_sw_modules()
1030 		struct cmac *mac = adapter->port[i].mac;  in t1_free_sw_modules()
1031 		struct cphy *phy = adapter->port[i].phy;  in t1_free_sw_modules()
1039 	if (adapter->sge)  in t1_free_sw_modules()
1040 		t1_sge_destroy(adapter->sge);  in t1_free_sw_modules()
1041 	if (adapter->tp)  in t1_free_sw_modules()
1042 		t1_tp_destroy(adapter->tp);  in t1_free_sw_modules()
1043 	if (adapter->espi)  in t1_free_sw_modules()
1044 		t1_espi_destroy(adapter->espi);  in t1_free_sw_modules()
1068 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)  in t1_init_sw_modules()  argument
1072 	adapter->params.brd_info = bi;  in t1_init_sw_modules()
1073 	adapter->params.nports = bi->port_number;  in t1_init_sw_modules()
1074 	adapter->params.stats_update_period = bi->gmac->stats_update_period;  in t1_init_sw_modules()
1076 	adapter->sge = t1_sge_create(adapter, &adapter->params.sge);  in t1_init_sw_modules()
1077 	if (!adapter->sge) {  in t1_init_sw_modules()
1079 		       adapter->name);  in t1_init_sw_modules()
1083 	if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {  in t1_init_sw_modules()
1085 		       adapter->name);  in t1_init_sw_modules()
1089 	adapter->tp = t1_tp_create(adapter, &adapter->params.tp);  in t1_init_sw_modules()
1090 	if (!adapter->tp) {  in t1_init_sw_modules()
1092 		       adapter->name);  in t1_init_sw_modules()
1096 	board_init(adapter, bi);  in t1_init_sw_modules()
1097 	bi->mdio_ops->init(adapter, bi);  in t1_init_sw_modules()
1099 		bi->gphy->reset(adapter);  in t1_init_sw_modules()
1101 		bi->gmac->reset(adapter);  in t1_init_sw_modules()
1103 	for_each_port(adapter, i) {  in t1_init_sw_modules()
1108 		adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,  in t1_init_sw_modules()
1110 		if (!adapter->port[i].phy) {  in t1_init_sw_modules()
1112 			       adapter->name, i);  in t1_init_sw_modules()
1116 		adapter->port[i].mac = mac = bi->gmac->create(adapter, i);  in t1_init_sw_modules()
1119 			       adapter->name, i);  in t1_init_sw_modules()
1127 		if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)  in t1_init_sw_modules()
1129 		else if (vpd_macaddress_get(adapter, i, hw_addr)) {  in t1_init_sw_modules()
1131 			       adapter->port[i].dev->name);  in t1_init_sw_modules()
1134 		eth_hw_addr_set(adapter->port[i].dev, hw_addr);  in t1_init_sw_modules()
1135 		init_link_config(&adapter->port[i].link_config, bi);  in t1_init_sw_modules()
1138 	get_pci_mode(adapter, &adapter->params.pci);  in t1_init_sw_modules()
1139 	t1_interrupts_clear(adapter);  in t1_init_sw_modules()
1143 	t1_free_sw_modules(adapter);  in t1_init_sw_modules()